Senior ASIC Design Verification Engineer – AI Compute

Persimmons, Inc.

. Own verification of the AI Persimmons inference chiplet .

Posted 10/17/2026full-timeSan Jose • California • United StatesSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in verification planning and execution for AI chiplet designs, utilizing advanced SystemVerilog, UVM, and C/C++ for firmware testing on RISC-V processors. Proven ability to lead teams in developing scalable verification flows and applying formal verification techniques to ensure high-quality outcomes.

Highest-signal resume keywords

Verification PlanningAdvanced SystemVerilogUVM Testbench DesignC/C++ Firmware DevelopmentAI-Driven Workflows

ATS Keywords

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Hard Skills

Verification ExperienceTest Plan DevelopmentSimulation Environment CreationComplex DebuggingFormal VerificationAssertion-Based VerificationCoverage-Driven StrategiesRISC-V Embedded Code DevelopmentFPGA PrototypingCompute Logic Validation

Soft Skills

CollaborationLeadershipProblem-SolvingHigh Ownership

Tools & Technologies

Synopsys HAPSAI AgentsEDA Tools

Industry Keywords

Electrical EngineeringComputer EngineeringSoCsIP BlocksDatapaths

Tech Stack

Tools & technologies

C++

About the role

Key responsibilities & impact

Own verification of the AI Persimmons inference chiplet
Lead verification planning and execution from subsystem to full chip
Collaborate with the CTO, design, algorithm, compiler, and software teams
Build test plans validating implementation against specifications
Design and implement portable UVM testbenches with constrained-random stimulus, compute reference models, and scoreboards
Drive code, functional, and formal coverage closure
Apply formal verification to compute logic
Develop and validate C/C++ firmware tests on RISC-V cores for end-to-end compute feature testing
Extend verification with FPGA prototyping on Synopsys HAPS
Enable software teams to run small real workloads
Use AI agents for testbench generation, stimulus creation, regression triage, log analysis, and coverage closure
Run efficient automated regressions, conserve EDA licenses, analyze bug trends, and drive bugs to closure

Requirements

What you’ll need

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline
5+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs
Verification experience on compute and fabric datapaths
Advanced SystemVerilog/Verilog and UVM
C/C++ embedded code development and validation on RISC-V or similar processors
Track record of scalable verification flows, coverage-driven strategies, assertion-based and formal verification, and data-driven decisions before tape-out
Experience building real AI-driven workflows, including writing instructions for agents and shipping automation, ideally for regression triage, log analysis, or testbench generation
Comfortable leading and working hands-on in a small, high-ownership team
Ability to work on site in San Jose

Benefits

Comp & perks

Competitive salary and benefits package
Flexible PTO
401k