System & Advanced Packaging Design Lead

PHIZENIX

. Direct Signal Integrity for package, PCB, and system design for copper interconnects beyond 200G .

Posted 10/12/2026full-timeSanta Clara • California • United StatesSenior💰 $180,000 - $200,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Signal Integrity and Power Integrity for advanced packaging and PCB design, with a strong focus on high-volume manufacturing and reliability. Proven ability to lead cross-functional teams in developing complex data-center solutions and micro-LED packaging.

Highest-signal resume keywords

Signal Integrity ExpertisePower Integrity ManagementAdvanced Packaging DevelopmentCross-Functional Team LeadershipHigh-Volume Manufacturing Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Signal Integrity AnalysisPower Integrity AnalysisChannel Simulation3D EM ExtractionThermal ModelingOptics PackagingJEDEC QualificationMicro-LED PackagingPAM4 Channel DesignFailure Analysis

Soft Skills

Cross-Functional CommunicationProgram DisciplineSchedule ManagementRisk ManagementTechnical Presentation

Tools & Technologies

HFSSQ3DSIwavePowerSIADSCadence APDAllegroIcepakFloTHERMVNA/TDR

Industry Keywords

High-Volume ManufacturingAdvanced CMOS NodesCo-Packaged OpticsUCIeChiplet PackagingThermo-Mechanical StressCrosstalk ControlLarge-Body PackagesSilicon-PhotonicsActive Alignment

About the role

Key responsibilities & impact

Direct Signal Integrity for package, PCB, and system design for copper interconnects beyond 200G
Enable advanced packaging for driver, TIA, and optics for AI scale-up engines, including signal integrity, power integrity, reliability, thermals, and high-volume manufacturing
Drive micro-LED packaging and heterogeneous package development
Develop complete data-center solutions with the OSAT ecosystem
Own package, PCB, and system-level SI architecture for 200G+/lane copper interconnects from channel budgeting and topology definition through post-layout signoff and silicon-measurement correlation
Drive 2.5D/3D and heterogeneous package development for co-packaged driver, TIA, and optical engines
Lead micro-LED and photonic packaging development, including optical coupling, alignment, hermeticity, reliability, and thermal co-design
Define and manage OSAT and substrate supplier strategy, including technology selection, DFM reviews, JEDEC qualification, yield ramp, and HVM readiness
Own package-level power integrity and thermal strategy, including PDN targets, decoupling plans, lid/TIM selection, and signoff criteria
Coordinate execution across silicon design, product/test engineering, systems hardware, and manufacturing partners; run design reviews and manage schedule and risk
Drive substrate stackup definition, ballmap/pinmap optimization, and high-density breakout and escape routing studies
Perform 3D EM extraction, channel simulation, S-parameter quality checks, and COM/IL/RL budgeting against IEEE 802.3 and OIF-CEI specifications
Build and correlate PDN and thermal models across die, package, and board
Lead lab characterization using VNA/TDR measurements, BER and eye-margin testing, model-to-measurement correlation, and failure-analysis support
Author package design guidelines, review checklists, and reference collateral

Requirements

What you’ll need

Ph.D. in Electrical Engineering (or related) with 5+ years, OR M.S. with 8+ years of advanced package development in high volume
Proven experience leading teams to successful execution, with multiple products delivered in advanced CMOS nodes
Deep SI/PI expertise for multi-GHz serial links: 112G/224G PAM4 channel design, COM analysis, crosstalk and mode-conversion control, and connector/cable interfaces
Advanced packaging depth: FCBGA, RDL/fan-out, 2.5D interposers and silicon bridges, substrate design rules, and materials selection
Fluency with HFSS, Q3D, SIwave/PowerSI, ADS channel simulation, Cadence APD/Allegro (or equivalent), and thermal tools such as Icepak or FloTHERM
Reliability and qualification knowledge: JEDEC standards, moisture sensitivity, thermo-mechanical stress, and warpage/coplanarity management for large-body packages
Working knowledge of optics packaging: VCSEL/PD or silicon-photonics co-packaging, fiber and lens coupling, and active alignment concepts
Track record leading small internal teams and external partners through complete product cycles into volume production
Strong program discipline: schedule and risk management, structured design reviews, and clear documentation
Excellent cross-functional communication with silicon, systems, and executive stakeholders; comfortable presenting technical trade-offs to customers and partners
Experience with co-packaged optics, linear-drive optics, or active copper/electrical cable products
Micro-LED, VCSEL, or photonic device packaging experience
Familiarity with UCIe and chiplet/die-to-die interconnect packaging
Hands-on HVM ramp experience at leading OSATs
Prior startup experience or comfort operating with broad scope under resource constraints