Apply

Ready to go for it?

AI Apply speeds things up—apply directly if you prefer.

FREE ACCESS
5,000–10,000 jobs/day
Scoutfield Logo

See all jobs on Scoutfield

Search thousands of fresh jobs every day.

Discover
  • Fresh listings
  • Fast filters
  • No subscription required
Create a free account and start exploring right away.
Quadric

Staff Deep Learning Compiler Engineer

Quadric

. Design, implement, and maintain compiler optimization passes targeting Quadric’s processor architecture .

Posted 10/30/2026full-timeBurlingame • California • United StatesLead💰 $170,000 - $230,000 per yearWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in compiler optimization for deep learning frameworks, with a strong focus on performance enhancement through advanced techniques such as operator fusion and quantization. Proficient in C++ and Python, with extensive experience in developing and validating compiler infrastructures for various architectures.

Highest-signal resume keywords
C++ Proficiency (14/17/20)Python ProgrammingDeep Learning Compiler DevelopmentCompiler Frameworks (MLIR, LLVM, TensorRT)Low-Level Kernel Optimization

ATS Keywords

Tailor your resume
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills
Compiler OptimizationData StructuresAlgorithmsObject-Oriented DesignMemory Allocation StrategiesQuantization Techniques (INT8/FP8)Parallel ProcessingInstruction Execution (CPU/GPU/NPU)Benchmarking and ProfilingGraph-Level Optimizations
Tools & Technologies
PyTorchTensorFlowONNXFPGAASICApache TVMXLAGlowCustom AI AcceleratorsCycle-Accurate Simulators
Industry Keywords
Deep LearningCompiler InfrastructureMicro-ArchitectureHardware AccelerationEmbedded Architectures

Tech Stack

Tools & technologies
ApachePythonPyTorchTensorflowC++

About the role

Key responsibilities & impact
  • Design, implement, and maintain compiler optimization passes targeting Quadric’s processor architecture
  • Develop lowering pathways from PyTorch, TensorFlow, and ONNX to optimized low-level kernel code
  • Optimize neural network performance for memory throughput, latency, compute-unit utilization, and power consumption
  • Implement graph-level optimizations including operator fusion, layout transformation, quantization, and memory allocation strategies
  • Analyze Transformer, CNN, and Vision-Language Model topologies and extend compiler support for new operators and primitives
  • Benchmark and profile end-to-end model performance to identify and resolve compiler bottlenecks
  • Collaborate with hardware and micro-architecture teams on instruction-set extensions, hardware acceleration features, and compiler requirements
  • Develop software simulators, functional models, and test benches to validate compiler correctness and generated binary performance
  • Participate in hardware bring-up and validation on FPGA and ASIC platforms
  • Integrate key deep learning models into Quadric’s compiler pipeline
  • Implement custom graph and code-generation optimization passes delivering measurable benchmark improvements
  • Partner with the architecture team on next-generation micro-architecture definition through workload analysis

Requirements

What you’ll need
  • BS, MS, or Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field
  • 8+ years of hands-on experience developing deep learning compilers or compiler infrastructures
  • Strong proficiency in C++ (14/17/20) and Python
  • Solid fundamentals in data structures, algorithms, and object-oriented design
  • Familiarity with PyTorch, TensorFlow, ONNX, and deep learning operator representations
  • Solid understanding of computer systems, memory hierarchies, parallel processing, and CPU/GPU/NPU instruction execution
  • Experience with compiler frameworks such as MLIR, Apache TVM, LLVM, XLA, TensorRT, or Glow
  • Candidates must be authorized to work in the United States for this U.S.-based role
  • Preferred: experience with low-level kernel optimization, SIMD/vector programming, memory allocation strategies, INT8/FP8/mixed-precision quantization, post-training/QAT optimization, custom AI accelerators/DSPs/embedded architectures, FPGA bring-up, hardware emulation, or cycle-accurate simulator development

Benefits

Comp & perks
  • Medical, dental, and vision insurance from day one; premiums covered at 99% for employees
  • Company-paid life insurance
  • Voluntary supplemental life insurance
  • STD + LTD insurance
  • Commuter support including parking or Caltrain reimbursement
  • FSA + HSA
  • Equity with the business
  • Paid parental leave
  • 401(k) retirement plan
  • Flexible PTO
  • Winter holiday shutdown
  • Catered lunch each day in the office
  • Relocation support for candidates joining from outside the Bay Area
  • Collaborative, low-ego culture with significant ownership and impact
  • Work culture focused on innovative disruption
  • Discretionary annual performance bonus