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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in RTL coding with System Verilog, optimizing FPGA logic and timing, and managing the complete coding process from architecture to implementation. Collaborates effectively with multidisciplinary teams to ensure seamless hardware-software integration.
Highest-signal resume keywords
RTL CodingSystem VerilogFPGA OptimizationBSc In Electrical/Computer Engineering4+ Years Of Experience
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
RTL CodingSystem VerilogFPGA OptimizationArchitecture DesignMicroarchitecture Design
Soft Skills
CollaborationCommunication
Tools & Technologies
VCSVivado
Industry Keywords
Low-Latency DesignHardware-Software InterfaceQuantum Physics Collaboration
About the role
Key responsibilities & impact- Design configurable, very low-latency RTL
- Optimize FPGA logic and timing to push state-of-the-art FPGA capabilities
- Own the entire coding process end to end: architecture, microarchitecture, design, and implementation
- Learn system and software requirements for proper hardware-software interface implementation
- Collaborate closely with engineers from other disciplines and quantum physicists
Requirements
What you’ll need- BSc in electrical/computer engineering or relevant military background - MUST
- At least 4 years of experience - MUST
- Proven track record in RTL coding with System Verilog - MUST
- Experience with System Verilog - MUST
- VCS, Vivado - Advantage