ASIC Design Manager

Ralliant

. Lead, mentor, and develop a team of digital ASIC design, verification, and physical design engineers .

Posted 10/6/2026full-timeUnited StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in leading digital ASIC design and verification teams, managing end-to-end development processes, and applying advanced digital design methodologies. Proficient in physical design execution, project management, and collaboration with cross-functional teams to ensure successful ASIC development and production readiness.

Highest-signal resume keywords

Digital ASIC DevelopmentMicroarchitecture DesignStatic Timing AnalysisPhysical Design ImplementationTeam Leadership and Mentoring

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogVerilog RTLFloor-PlanningPower IntegrityClock-Tree SynthesisPlace-and-RouteTiming ClosureDFTSilicon ValidationMixed-Signal Design

Soft Skills

CommunicationCollaborationOrganizational SkillsProblem-Solving

Tools & Technologies

CadenceSynopsysSiemens EDAASIC Design ToolsEDA Suppliers

Industry Keywords

ASICDigital Integrated CircuitsTapeoutSilicon Bring-UpDesign ClosureElectromigration VerificationIR-Drop AnalysisChipletsAdvanced Packaging TechnologiesFPGA Prototyping

About the role

Key responsibilities & impact

Lead, mentor, and develop a team of digital ASIC design, verification, and physical design engineers
Own the end-to-end digital ASIC development flow from microarchitecture and RTL development through IP integration, physical design, signoff, tapeout, and silicon bring-up
Set technical direction for digital IP, subsystem design, full-chip integration, and physical implementation
Drive physical design planning and execution, including floorplanning, power-grid architecture, clock distribution, congestion analysis, routing optimization, engineering change orders, and design closure
Apply digital-on-top development flows for mixed-signal designs
Oversee signoff activities including static timing analysis, signal integrity, power integrity, IR-drop, electromigration, formal equivalence, DRC, LVS, and tapeout-readiness reviews
Partner with product and system architects to translate requirements into ASIC specifications, partitioning strategies, interfaces, and performance targets
Coordinate execution across UVM verification, DFT, CAD, packaging, validation, product engineering, foundry, and external design-services teams
Collaborate on die planning, bump assignments, power delivery, thermal performance, manufacturability, and package integration
Develop and execute project plans covering schedules, resources, costs, milestones, and risk mitigation
Drive design quality through methodologies, technical reviews, lint and CDC readiness, implementation checks, and signoff criteria
Improve design flows, automation, and engineering practices
Support silicon bring-up, characterization, post-silicon debug, and production-readiness activities
Manage contractors, external design-service providers, IP vendors, and technical partners
Contribute directly to technical reviews and critical design or implementation work

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, a related technical discipline, or equivalent practical experience
Significant experience developing ASICs or complex digital integrated circuits, including digital design and physical implementation activities
Experience leading technical projects, mentoring engineers, or coordinating work across multidisciplinary engineering teams
Strong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis
Experience with physical design and implementation, including several of: floor-planning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff
Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs
Experience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers
Experience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production release
Strong communication, collaboration, organizational, and problem-solving skills
Preferred: experience managing or formally leading engineering teams, including hiring, coaching, career development, and resource planning
Preferred: Master’s or doctoral degree in Electrical Engineering, Computer Engineering, or a related field
Preferred: experience leading end-to-end digital ASIC or SoC implementation through tapeout
Preferred: experience with high-speed digital or mixed-signal ASICs, DSP architectures, data-converter interfaces, or instrumentation applications
Preferred: experience with multi-mode, multi-corner timing analysis, signal-integrity analysis, IR-drop and electromigration verification, or other physical signoff methodologies
Preferred: experience optimizing designs for performance, power, area, yield, reliability, and manufacturability
Preferred: familiarity with flip-chip packaging, bump planning, package co-design, multi-chip modules, chiplets, or advanced packaging technologies
Preferred: experience with FPGA prototyping, emulation, or pre-silicon validation methods
Preferred: experience collaborating with foundries, OSAT partners, external IP vendors, EDA suppliers, or design-services providers
Preferred: experience improving ASIC development methodologies, automation, and team execution practices

Benefits

Comp & perks

Opportunity to shape the future of Tektronix instrumentation platforms
Lead a talented engineering team responsible for strategic silicon development
Influence technology direction, engineering methodology, and program execution
Professional growth and continuous learning opportunities
Collaborative engineering culture
Recruit and retain engineering talent, with responsibility for career growth and development