Digital IC Design Verification Engineer

Snap Inc.

. Work as part of a multi-disciplinary team designing display ICs for AR .

Posted 10/7/2026full-timeWashington • United StatesMid-LevelSenior💰 $173,000 - $259,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in custom layout design for analog and mixed-signal circuits, utilizing tools such as Cadence Virtuoso and Mentor/Siemens Calibre. Proficient in scripting and automation to enhance design efficiency and ensure compliance with foundry requirements.

Highest-signal resume keywords

Custom Transistor-Level LayoutCadence Virtuoso Tool SuiteMentor/Siemens Calibre Tool SuiteScripting and Automation (TCL, SKILL, Perl, Python, Shell)Signal Integrity and Layout Effects

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Custom Layout DesignAnalog Circuit FunctionsCell and Block LayoutParasitic ExtractionDRC, ERC, LVS VerificationFoundry DFM RequirementsSRAM DesignPLL DesignADC DesignDAC Design

Soft Skills

CollaborationCommunicationPresentation Skills

Tools & Technologies

Cadence VirtuosoMentor/Siemens CalibreLinux Environment

Certifications & Qualifications

BSEE or Relevant Experience

Industry Keywords

Display ICsAR TechnologyMixed-Signal CircuitsCMOS Foundry DesignASIC IC Test and Characterization

Tech Stack

Tools & technologies

LinuxNode.jsPerlPython

About the role

Key responsibilities & impact

Work as part of a multi-disciplinary team designing display ICs for AR
Collaborate with digital and analog logic, circuit and physical design engineers and other custom layout engineers
Perform cell and block layout of analog and mixed-signal circuit functions while meeting design rules and performance requirements
Create reusable scripts and methodologies to automate design flow, repeatability and efficiency
Implement circuit layout strategies for optimal area, performance and power goals
Support IC floor planning and place-and-route of full-chip digital designs with digital and analog IP
Provide schedule and cost inputs to program management
Create and present design documentation for internal design reviews
Execute parasitic extraction of circuit layout and iterate design improvements

Requirements

What you’ll need

BSEE or relevant years of experience
5+ years in directly applicable work performing custom layout
Strong working knowledge of custom transistor-level layout, including matching techniques
Strong working knowledge of Cadence Virtuoso (Layout and Schematic) tool suite
Strong working knowledge of Mentor/Siemens Calibre tool suite (DRC, LVS, Extraction)
Scripting and automation using TCL, SKILL, Perl, Python and Shell scripts in Linux environment
Experience executing project tape out verification including DRC, ERC and LVS
Extensive understanding of signal integrity, reliability, layout effects (EM, IR drop) and related considerations
Knowledge of tool flows and techniques for achieving foundry DFM requirements
Prior detailed design and custom layout experience with designs such as SRAM, level shifters, IO design (ESD, latch-up), PLLs, Bandgaps, ADCs, DACs and amplifiers
Preferred: detailed understanding of 22nm and below CMOS foundry design node rules and requirements
Preferred: experience with both Analog and Memory layouts
Preferred: knowledge of ASIC IC test and characterization
Preferred: understanding of digital design and place-and-route principles

Benefits

Comp & perks

Paid parental leave
Comprehensive medical coverage
Emotional and mental health support programs
Compensation packages including equity in the form of RSUs
Default Together approach with in-office work 4+ days per week