Integrated Circuit Design Verification Engineer

Snap Inc.

. Design display Integrated Circuits for augmented reality as part of a multi-disciplinary team .

Posted 10/7/2026full-timeWashington • United StatesSeniorLead💰 $173,000 - $259,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in ASIC Design Verification with a strong focus on UVM and SystemVerilog, complemented by extensive experience in digital functional simulation and verification processes. Proficient in scripting and automation within a Linux environment, with a solid understanding of video and display systems and relevant protocols.

Highest-signal resume keywords

ASIC Design VerificationUVM and SystemVerilogSiemens Questa ToolsScripting and AutomationDigital Functional Simulation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC Design VerificationUVMSystemVerilogVerilog RTL CodingTCL ScriptingMake ScriptingPerl ScriptingPython ScriptingShell ScriptingDigital Functional Simulation

Soft Skills

Excellent CommunicationOrganizational SkillsMultitaskingPrioritization

Tools & Technologies

Siemens QuestaUVM Framework

Certifications & Qualifications

BSEEMSEE

Industry Keywords

Verification Test PlansFunctional CoverageCode CoverageEmulationRTL DesignMIPIAMBAI2CSPIEmbedded Microcontrollers

Tech Stack

Tools & technologies

LinuxPerlPython

About the role

Key responsibilities & impact

Design display Integrated Circuits for augmented reality as part of a multi-disciplinary team
Collaborate with digital design, analog logic, software, and verification engineers
Develop and implement UVM-based and assertion-based testbenches
Create and execute verification test plans, including functional coverage and code coverage
Use Siemens Questa tools for verification and debugging
Specify and configure tools and create automation

Requirements

What you’ll need

BSEE or MSEE or relevant years of experience
10+ years of experience in ASIC Design Verification
Strong knowledge of UVM and SystemVerilog
Strong knowledge of digital functional simulation and Siemens Questa
Strong knowledge of Verilog RTL coding practices
Scripting and automation using TCL, Make, Perl, Python, and Shell scripts in a Linux environment
Excellent written and verbal English communication
Experience with the entire verification process from planning to sign-off
Experience with Siemens’ UVM Framework
Experience in emulation
Experience in RTL design
Familiarity with video and display systems, MIPI, AMBA, I2C, SPI protocols, and embedded microcontrollers
Familiarity with ASIC test or production flow
Ability to organize complex issues and drive them to closure
Ability to multitask and prioritize

Benefits

Comp & perks

Paid parental leave
Comprehensive medical coverage
Emotional and mental health support programs
Compensation packages including equity in the form of RSUs
Equal opportunity employment protections
Criminal history consideration consistent with applicable law