Digital IC Design Verification Engineer

SNAP/SNAP

. Work as part of a multi-disciplinary team designing display ICs for AR .

Posted 10/7/2026full-timeWashington • United StatesMid-LevelSenior💰 $173,000 - $259,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in custom layout design for analog and mixed-signal circuits, utilizing tools such as Cadence Virtuoso and Mentor/Siemens Calibre. Proficient in scripting and automation to enhance design efficiency and ensure compliance with foundry requirements.

Highest-signal resume keywords

Custom Layout DesignCadence VirtuosoMentor/Siemens CalibreScripting and AutomationSignal Integrity

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Custom Transistor-Level LayoutDRC, LVS, and ExtractionTCL ScriptingSKILL ScriptingPerl ScriptingPython ScriptingShell ScriptingProject Tape-Out VerificationSignal Integrity AnalysisFoundry DFM Requirements

Soft Skills

Technical DocumentationVerbal Communication

Tools & Technologies

Cadence Virtuoso LayoutMentor/Siemens Calibre Tool SuiteLinux Environment

Industry Keywords

Analog and Mixed-Signal CircuitsIC Floor PlanningPlace-and-RouteSRAM DesignLevel ShiftersIO DesignPLLsADCsDACsAmplifiers

Tech Stack

Tools & technologies

LinuxNode.jsPerlPython

About the role

Key responsibilities & impact

Work as part of a multi-disciplinary team designing display ICs for AR
Collaborate with digital and analog logic, circuit and physical design engineers, and custom layout engineers
Perform cell and block layout of analog and mixed-signal circuit functions while meeting design rules and performance requirements
Create reusable scripts and methodologies to automate design flow, repeatability, and efficiency
Implement circuit layout strategies for optimal area, performance, and power
Support IC floor planning and place-and-route of full-chip digital designs with digital and analog IP
Provide schedule and cost inputs to program management
Create and present design documentation for internal design reviews
Execute parasitic extraction of circuit layout and iterate design improvements

Requirements

What you’ll need

BSEE or relevant years of experience
5+ years in directly applicable work performing custom layout
Strong working knowledge of custom transistor-level layout, including matching techniques
Strong working knowledge of Cadence Virtuoso Layout and Schematic tool suite
Strong working knowledge of Mentor/Siemens Calibre tool suite, including DRC, LVS, and extraction
Scripting and automation using TCL, SKILL, Perl, Python, and Shell scripts in a Linux environment
Experience executing project tape-out verification, including DRC, ERC, and LVS
Extensive understanding of signal integrity, reliability, layout effects including EM and IR drop
Knowledge of tool flows and techniques for achieving foundry DFM requirements
Prior detailed design and custom layout experience with designs such as SRAM, level shifters, IO design, PLLs, bandgaps, ADCs, DACs, and amplifiers
Preferred: detailed understanding of 22nm and below CMOS foundry design node rules and requirements
Preferred: experience with both analog and memory layouts
Preferred: excellent technical, documentation, and verbal skills
Preferred: knowledge of ASIC IC test and characterization
Preferred: understanding of digital design and place-and-route principles

Benefits

Comp & perks

Paid parental leave
Comprehensive medical coverage
Emotional and mental health support programs
Compensation packages including equity in the form of RSUs
Default together approach with in-office work 4+ days per week