Package Design Engineer

SPD Technology

. Develop physical package substrate designs for large form-factor packages for ML high-performance computers (HPCs) .

Posted 10/15/2026full-timeRemote • Mexico, Netherlands, Germany, France, United Kingdom, IsraelSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in chip package substrate design, including layout, verification, and advanced packaging technologies. Proficient in collaborating with cross-functional teams and managing design automation processes to enhance productivity and efficiency.

Highest-signal resume keywords

Chip Package Substrate DesignCadence APDDesign Automation2.5D/3.5D Advanced Package DesignPhysical Verification Flow

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Chip Package Substrate LayoutDesign VerificationDFMTaping Out for ProductionScriptingRouting Feasibility StudiesTest Vehicle DevelopmentFinal Manufacturing DocumentationBill of Materials (BOM)Mechanical Drawings

Soft Skills

CollaborationCross-Functional Teamwork

Tools & Technologies

Mentor ExpeditionCADSI/PI ToolsPCB Design Tools

Industry Keywords

High-Performance Computers (HPCs)Advanced Chip Packaging TechnologiesData Center EnvironmentsPPATCO

Tech Stack

Tools & technologies

Assembly

About the role

Key responsibilities & impact

Develop physical package substrate designs for large form-factor packages for ML high-performance computers (HPCs)
Develop and implement methodology and CAD flow for efficient substrate design and enhanced productivity
Manage and drive co-design initiatives across chip, package, and system levels
Secure production sign-off for package designs
Collaborate with SI/PI, thermal, mechanical, assembly, and PCB engineering teams
Refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility
Manage routing feasibility studies, test vehicle development, product-level designs, design reviews, artwork export, DFM activities, and final manufacturing documentation
Define and document package substrate design requirements and bill of materials (BOM)
Contribute to evaluation and adoption of advanced chip packaging technologies
Support deployment of advanced computing systems in large-scale data center environments and optimize PPA and TCO

Requirements

What you’ll need

Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience
8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition
Experience in chip package substrate layout, design verification, DFM, and taping out for production
Experience in design automation and scripting
English — Upper Intermediate or higher
Experience working with cross-functional teams including chip design, SI/PI, and PCB design teams
Experience in 2.5D/3.5D advanced package design
Experience in physical verification flow (LVS, DRC, connectivity)
Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD)
Ability to write scripts to customize elements of the Cadence or Mentor workflow

Benefits

Comp & perks

Fully remote work around the globe
Hybrid work model available from office hubs
Flexible working schedule
Stable workload and stable income
Performance review and career path
Mentorship program
Personal development plan
Individual learnings through the corporate library
Public speaking support
Company-wide tech and cultural events
Meaningful CSR initiatives
Supportive work environment with collaboration, open communication, and mutual respect