Signal and Power Integrity Engineer

SPD Technology

. Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) using advanced 2.5D/3D packaging technologies .

Posted 10/15/2026contractRemote • Israel, United Kingdom, France, Germany, Netherlands, MexicoSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in Signal Integrity (SI) and Power Integrity (PI) analysis and optimization for High-Performance Computing (HPC) is essential, along with proficiency in industry-standard modeling tools and programming languages for automated data processing. Strong collaboration skills with cross-functional teams are critical for successful product development and validation.

Highest-signal resume keywords

Signal Integrity (SI) AnalysisPower Integrity (PI) AnalysisHigh-Speed Interface IP EvaluationPython ProgrammingSIPI Modeling Tool Chains

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Signal Integrity (SI) DesignPower Integrity (PI) DesignHigh-Speed Memory InterfacesStatic Timing Analysis (STA)DFM Constraints ManagementChip FloorplanningSimulation MethodologiesData Processing ToolsTiming Budget Methodologies3D Die Stacking Architectures

Soft Skills

CollaborationInfluencingCommunicationProblem-SolvingTeam Partnership

Tools & Technologies

HFSSADSSigritySiwaveTest Environments

Industry Keywords

High-Performance Computing (HPC)Chip ArchitectureSilicon InterposersSilicon BridgesSerDesHBMxD2D/ChipletsNPI ValidationElectrical EngineeringComputer Architecture

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) using advanced 2.5D/3D packaging technologies
Partner early in product definition to influence chip floorplanning, power distribution networks, power trees, netlists, and routability tradeoffs
Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries
Drive post-silicon validation and qualification for NPI
Balance SI/PI performance and DFM constraints to achieve final package design closure
Partner with silicon, system, and external vendor teams
Develop simulation methodologies to improve modeling accuracy and efficiency
Collaborate with Chip Design, IP, System Design, software, and vendor teams

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
8 years of experience in SI/PI design for chip/package or system PCB
Experience in industry SIPI modeling tool chains, such as HFSS, ADS, Sigrity, and Siwave
Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes
Experience partnering across chip architecture, physical design, static timing analysis (STA), package, and validation teams
Experience in Python, MATLAB, or C++ for automated flows and data processing tools
Deep knowledge of SI/PI analysis for high-speed interconnects such as HBMx, D2D/chiplets, PCIe, and SerDes, and timing budget methodologies
Direct experience with silicon interposers, silicon bridges, and 3D die stacking architectures is a bonus
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture, is a bonus

Benefits

Comp & perks

Fully remote around the globe or hybrid work model from office hubs
Flexible working schedule
Stable workload and stable income
Performance review and career path
Mentorship program
Personal development plan
Individual learnings through the corporate library
Public speaking support
Company-wide tech and cultural events
Meaningful CSR initiatives
Supportive and flexible work environment
Collaboration, open communication and mutual respect