Datacenter Engineer – Agentic AI Workload Performance Optimization

Tenstorrent Inc.

. Optimize software workloads running on next-generation RISC-V platforms .

Posted 10/30/2026full-timeRemote • California • United States, CanadaMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in performance optimization and computer architecture, with strong programming skills in Java, Python, C/C++, and RISC-V assembly. Proficient in using performance profiling tools and optimizing software workloads on RISC-V platforms.

Highest-signal resume keywords

Performance OptimizationRISC-V ArchitectureCompiler OptimizationPerformance Profiling ToolsProgramming in Java, Python, C/C++

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Performance OptimizationRISC-V ArchitectureCompiler OptimizationProgramming in JavaProgramming in PythonProgramming in C/C++RISC-V AssemblyVector/SIMD OptimizationConcurrency ManagementGarbage Collection

Tools & Technologies

OpenJDK/JITLLVMGCCV8Linux PerfQEMUTracing ToolsPerformance Modeling Environments

Industry Keywords

Computer EngineeringElectrical EngineeringComputer ScienceDatacenter WorkloadsAI WorkloadsMemory HierarchiesRuntime OptimizationExport-Controlled Technology

Tech Stack

Tools & technologies

AssemblyJavaJavaScriptLinuxLuaNode.jsPHPPythonRustC++Go

About the role

Key responsibilities & impact

Optimize software workloads running on next-generation RISC-V platforms
Work across modern datacenter and agentic AI workloads, including Java, Python, PHP, Node.js, Lua, Go, and Rust
Identify performance bottlenecks and develop software, compiler, runtime, and hardware-aware optimizations
Improve throughput, latency, and efficiency
Bring up and tune major runtimes
Profile real-world applications and investigate memory and concurrency behavior
Explore optimizations using RISC-V Vector/Matrix capabilities and custom instructions
Use AI-assisted development and automated optimization workflows
Collaborate across compiler, runtime, systems software, hardware, and performance modeling teams
Influence the RISC-V software ecosystem and future Tenstorrent CPU architecture

Requirements

What you’ll need

Master’s or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field, with strong experience in performance optimization, computer architecture, compilers, or systems software
Hands-on experience with runtime or compiler optimization, such as OpenJDK/JIT, LLVM, GCC, V8, Python, or equivalent systems
Strong understanding of CPU performance, memory hierarchies, concurrency, garbage collection, vector/SIMD optimization, and RISC-V architecture
Expertise with performance profiling and analysis tools such as Linux perf, runtime profilers, QEMU, tracing tools, and performance modeling environments
Strong programming skills in Java, Python, C/C++, and RISC-V assembly
Hands-on experience optimizing software on RISC-V or another modern CPU architecture
Eligibility to access U.S. export-controlled technology, including compliance with applicable U.S. export laws and potential citizenship, permanent residency, or prior license approval requirements

Benefits

Comp & perks

Compensation package and benefits
Variable compensation targets included in stated total compensation
Equal opportunity employer