Front End Design Verification Engineer

Tenstorrent Inc.

. Verify the fetch unit for next-generation high-performance RISC-V CPU cores .

Posted 10/31/2026full-timeRemote • California • United StatesMid-LevelSenior💰 $100,000 - $500,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in design verification for CPUs and complex digital designs, with strong capabilities in SystemVerilog, UVM, and debugging RTL failures. Proficient in collaborating across multidisciplinary teams to ensure front-end correctness and compliance with export regulations.

Highest-signal resume keywords

Design VerificationSystemVerilogUVMCPU ArchitectureC/C++ Programming

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Applicant Tracking System Keywords

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Hard Skills

Design VerificationSystemVerilogUVMCPU ArchitectureDebugging RTLC/C++ ProgrammingPython ProgrammingConstrained-Random TestingAssertionsFunctional Coverage

Soft Skills

CollaborationEffective Communication

Tools & Technologies

Simulation ToolsDebug Tools

Industry Keywords

RISC-VSoCsASICsHigh-Performance ComputingAIHPCExport Compliance

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Verify the fetch unit for next-generation high-performance RISC-V CPU cores
Develop verification strategies and sophisticated tests
Debug complex failures and ensure front-end correctness across workloads and corner cases
Collaborate closely with CPU architects, RTL designers, and other design verification engineers
Verify instruction fetch, prediction, decode, and dispatch logic
Verify speculative execution and corner cases involving branches, redirects, exceptions, and pipeline flushes
Translate architectural specifications and microarchitectural designs into RTL and comprehensive verification environments
Support processors designed for AI, HPC, and high-performance computing workloads

Requirements

What you’ll need

6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs
Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development
Solid understanding of CPU architecture, including pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution
Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools
Strong programming skills in C/C++ and/or Python
Ability to collaborate effectively across architecture, RTL, DV, and software teams
Eligibility to access U.S. export-controlled technology, including compliance with applicable export laws and possible citizenship/permanent residency or license requirements

Benefits

Comp & perks

Highly competitive compensation package and benefits