Midcore Design Verification Engineer

Tenstorrent Inc.

. Verify the next generation of high-performance RISC-V CPU cores .

Posted 10/31/2026full-timeRemote • SpainMid-LevelSenior💰 $100,000 - $500,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive experience in design verification for CPUs and complex digital designs, with strong capabilities in SystemVerilog, UVM, and debugging RTL failures. Proven ability to collaborate effectively with cross-functional teams throughout the design lifecycle.

Highest-signal resume keywords

Design VerificationSystemVerilogUVMDebugging RTLC/C++ or Python Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Design VerificationSystemVerilogUVMConstrained-Random TestingAssertionsFunctional CoverageDebugging RTLSimulation ToolsTestbench DevelopmentCPU Architecture

Soft Skills

CollaborationProblem-SolvingCommunication

Tools & Technologies

Simulation ToolsDebug Tools

Industry Keywords

CPUSoCASICDigital DesignOut-of-Order ExecutionPipelinesCachesLoad/StoreBranch PredictionInstruction Scheduling

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Verify the next generation of high-performance RISC-V CPU cores
Work closely with CPU architects, RTL designers, and software engineers
Develop verification strategies
Build robust test environments and test benches
Develop test plans
Perform constrained-random testing, assertions, and functional coverage
Debug RTL and simulation failures using waveforms and simulation/debug tools
Uncover important corner cases in modern out-of-order processors
Own meaningful portions of the verification effort
Drive issues to closure
Collaborate throughout the design lifecycle from specification through silicon

Requirements

What you’ll need

6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs
Strong experience with SystemVerilog and UVM, including testbench development, constrained-random testing, assertions, and functional coverage
Understanding of CPU architecture and/or microarchitecture, including concepts such as pipelines, out-of-order execution, caches, load/store, branch prediction, or instruction scheduling
Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools
Strong C/C++ or Python skills
Ability to work effectively with RTL designers, architects, and other verification engineers
Eligible to access U.S. export-controlled technology, or able to obtain required license approval where applicable

Benefits

Comp & perks

Highly competitive compensation package
Benefits