Mixed Signal IC Layout Engineer

Tenstorrent Inc.

. Execute full-custom analog/mixed-signal layout for key blocks from schematics to manufacturable layouts .

Posted 10/31/2026full-timeRemote • California • United StatesSeniorLead💰 $100,000 - $500,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in full-custom analog/mixed-signal layout, including proficiency in high-speed block design and physical verification. Capable of optimizing layouts for performance metrics while collaborating effectively with circuit designers.

Highest-signal resume keywords

Analog/Mixed-Signal IC Layout EngineeringFull-Custom Layout DesignSynopsys Custom CompilerCadence VirtuosoDRC, LVS, ERC, DFM Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Full-Custom LayoutHigh-Speed Block DesignCMOS/FinFET TechnologyEM/IR AnalysisSilicon Delivery ExperiencePost-Layout ExtractionSimulation SupportPython ScriptingTcl ScriptingSKILL Language

Soft Skills

CollaborationIndependent Ownership

Tools & Technologies

Synopsys ICVSiemens Calibre

Certifications & Qualifications

BSEE or Equivalent Experience

Industry Keywords

D2D PHY IntegrationPLLsVCOsADCsDACsLDOsComparatorsClock GeneratorsHigh-Speed I/OsExport-Controlled Technology

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Execute full-custom analog/mixed-signal layout for key blocks from schematics to manufacturable layouts
Develop optimized block and top-level floorplans, placement, and routing
Balance area, parasitics, matching, congestion, and integration into the D2D PHY
Optimize resistance/capacitance parasitics, coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals
Close DRC, LVS, ERC, DFM, and Antenna requirements
Support post-layout extraction and simulation
Contribute layout methodology and automation scripts using Python, Tcl, SKILL, etc. as a bonus
Integrate high-speed analog/mixed-signal IP into complex D2D PHYs across digital, analog, and I/O domains

Requirements

What you’ll need

Experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks, including PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, and high-speed I/Os
Proficient with Synopsys Custom Compiler or Cadence Virtuoso
Proficient with Synopsys ICV or Siemens Calibre for DRC, LVS, ERC, DFM, and Antenna physical verification
Deep experience in CMOS/FinFET nodes, ideally TSMC or Samsung 12nm–2nm
Delivered silicon experience
Strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts
Typically hold a BSEE or equivalent experience
Approximately 10+ years in analog/mixed-signal layout
Able to own complex blocks independently and collaborate effectively with circuit designers
Eligible to access U.S. export-controlled technology; employment may depend on citizenship/permanent residency status or prior license approval

Benefits

Comp & perks

Highly competitive compensation package
Benefits
Equal opportunity employer