Physical Design CPU Methodology Engineer

Tenstorrent Inc.

. Define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification .

Posted 10/31/2026full-timeRemote • California • United StatesSeniorLead💰 $100,000 - $500,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates extensive expertise in ASIC/SoC/CPU physical design methodology, including RTL-to-GDS implementation, timing closure, and power optimization. Proven ability to drive automation and collaborate with cross-functional teams to enhance design processes and productize AI/ML technologies.

Highest-signal resume keywords

ASIC/SoC/CPU ExperienceRTL-To-GDS ImplementationPhysical Design MethodologyTcl, Python, Perl ProficiencyTechnical Leadership

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SynthesisFloorplanningPower PlanningPlace And RouteCTSExtractionSTASIEM/IRPhysical Verification

Soft Skills

MentoringInfluencing Across Teams

Tools & Technologies

AI/ML-Enabled Physical Design ToolingAutomation ToolsCAD Flows

Certifications & Qualifications

Eligibility For U.S. Export-Controlled Technology

Industry Keywords

High-Performance CPUsDigital DesignsTiming ClosurePower OptimizationQuality MetricsSignoff CriteriaDebug Workflows

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification
Explore AI/ML-enabled physical design tooling
Begin synthesis and place-and-route of CPU partitions
Develop the new program RM flow
Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows
Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to enable advanced nodes and productize AI/ML across physical design

Requirements

What you’ll need

10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs or similarly complex digital designs
Deep expertise across RTL-to-GDS implementation and signoff, including timing closure, power optimization, SI, EM/IR, extraction, and physical verification
Experience building or owning physical design methodology, automation, or CAD flows
Proficiency in Tcl, Python, Perl, or similar scripting languages
Technical leadership ability to influence across teams, mentor engineers, and drive standards across geographically distributed organizations
Eligibility to access U.S. export-controlled technology, including compliance with applicable U.S. export laws and potential citizenship/permanent residency or prior license requirements

Benefits

Comp & perks

Highly competitive compensation package and benefits