Verification Engineer

Ubitium

. Build cocotb-based testbenches for RTL blocks, from complicated datapaths to multilevel interconnect .

Posted 10/5/2026full-timeKarlsruhe • GermanyJuniorMid-LevelWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in building cocotb-based testbenches and driving verification through property-based test generation. Proficient in SystemVerilog Assertions and RTL debugging, with a strong focus on functional coverage and collaboration with design teams.

Highest-signal resume keywords

SystemVerilogProperty Based VerificationRTL DebuggingSystemVerilog AssertionsPython

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Hard Skills

Cocotb-Based TestbenchesFunctional Coverage ClosureDebugging FailuresWriting Cover Property StatementsCross-Checking RTL Behavior

Soft Skills

CollaborationDocumentation

Tools & Technologies

GitWaveform ViewersSimulation Tools

Certifications & Qualifications

Master’s Degree

Industry Keywords

Formal VerificationVerification InfrastructureTest HarnessesCoverage Tooling

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Build cocotb-based testbenches for RTL blocks, from complicated datapaths to multilevel interconnect
Drive verification through property-based test generation rather than fixed directed vectors
Write SystemVerilog Assertions to catch protocol violations in simulation
Write cover property statements to close functional-coverage gaps
Cross-check RTL behavior against independent golden reference models, including formally specified models
Drive functional coverage closure and review coverage reports
Debug failures using waveform viewers and simulator transcripts
Trace failing assertions or model mismatches to root causes in RTL, testbench, or model
Document and track open verification findings with clear reproduction steps
Continuously improve verification infrastructure, including build flows, test harnesses, and coverage tooling
Collaborate directly with architects and designers to resolve findings

Requirements

What you’ll need

Languages: SystemVerilog, SystemVerilog Assertions, Python
Skills: RTL debugging, Property Based Verification, Git
Master’s degree (or equivalent)
2+ years of hands-on experience in a relevant role
Formal Verification exposure is good to have
Relocation required

Benefits

Comp & perks

Competitive salary plus stock options
30+ days of paid vacation
Relocation support
Full German social security and universal healthcare
A modern office
Free snacks, coffee, and drinks
Space to grow and shape your own path
Hands-on work with real implementations of AI and signal processing
Inclusive team culture where different perspectives are valued
Verification methodology you help shape
Direct, tight feedback loops with architects and designers
Exposure across the full stack of a RISC-V SoC