Staff Design Engineer, IC Layout

University of Washington, Department of Electrical & Computer Engineering

. Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for high-performance RF and ultra-low-power, compact RFID .

Posted 11/4/2026full-timeRemote • United StatesLead💰 $136,000 - $204,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in transistor-level layout for RF, mixed-signal, and analog circuits, with a strong understanding of semiconductor manufacturing processes and layout-dependent effects. Proficient in collaborating with design teams and managing technical projects to deliver high-performance RFID products.

Highest-signal resume keywords

Custom Analog LayoutRF Layout ExperienceCadence Virtuoso ProficiencyTechnical Project ManagementSemiconductor Manufacturing Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Transistor-Level LayoutMixed-Signal Circuit DesignAnalog Circuit DesignPower/Ground RoutingSignal IntegrityNoise Coupling ManagementParasitic ManagementLayout-Dependent EffectsGuard Rings MitigationEMIR and ESD Techniques

Soft Skills

Excellent CommunicationCollaboration SkillsProblem-Solving Ability

Tools & Technologies

Cadence VirtuosoCadence/Siemens Layout Verification ToolsPVSSiemens Calibre DRC/LVS

Industry Keywords

RFIDAnalog Circuit BlocksMixed-Signal LayoutElectromigrationSignal CouplingExport Control ComplianceFoundry TechnologiesAdvanced Process Nodes

About the role

Key responsibilities & impact

Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for high-performance RF and ultra-low-power, compact RFID
Work with analog and digital design teams on floor planning, pin placement, power supply strategy, and signal distribution between blocks
Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling
Participate in schedule meetings coordinating layout and floorplan activities
Deliver tape-outs for RFID products, test chips, reader ICs, and design-of-experiments work
Collaborate internationally with the analog RFID endpoint IC development team and Reader IC team

Requirements

What you’ll need

Bachelor’s degree in computer or electrical engineering
8+ years of experience
Experience in custom analog, RF, and mixed-signal layout
Ability to collaborate with layout engineers on top-level IC floorplans and partner with circuit designers to resolve complex problems
Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm
Knowledge of analog layout challenges and layout-dependent effects, including noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring
Knowledge of mitigation techniques including guard rings, DNW, PN junctions, parasitic management, signal integrity, EMIR, and ESD
Proficiency with Cadence Virtuoso layout editor
Proficiency with Cadence/Siemens layout verification tools, including PVS and Siemens Calibre DRC/LVS
Ability to interpret and correct ERC, DRC, and LVS error reports
Excellent communication and collaboration skills
Strong technical project management skills
Must satisfy applicable U.S. export control requirements; additional national identity documentation may be required to determine export authorization

Benefits

Comp & perks

Merit increases for eligible roles
Annual bonus for eligible roles
Stock for eligible roles
Sales incentives for eligible roles, depending on plan and role
Healthcare benefits for US-based employees
401(k) plan and company match
Support for remote work
Open paid-time-off policy
Work/life balance support
Weekly Q&A sessions with the executive team
Competitive benefits
Reasonable accommodation for individuals with disabilities