FPGA Engineer – Chip Design

Weekday (YC W21)

. Develop realistic engineering evaluation tasks covering RTL design, functional verification, synthesis, physical design, and sign-off .

Posted 10/11/2026full-timeRemote • IndiaMid-LevelSenior💰 ₹1,200,000 - ₹2,000,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in RTL Development, Design Verification, and EDA Tool Utilization, with a strong focus on evaluating and improving digital design workflows. Proficient in scripting for automation and capable of diagnosing and resolving design issues effectively.

Highest-signal resume keywords

RTL Development in Verilog, SystemVerilog, or VHDLDesign Verification and Testbench DevelopmentEDA Tools Proficiency (Synopsys, Cadence, Siemens, AMD/Xilinx, Intel)Static Timing Analysis and Timing ClosureDebugging and Problem-Solving Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DevelopmentDesign VerificationTestbench DevelopmentStatic Timing AnalysisTiming ClosureLogic SynthesisPlace-and-RoutePower, Performance, and Area (PPA) EvaluationScripting in Python, Tcl, or PerlUVM Methodologies

Soft Skills

Analytical SkillsProblem-Solving SkillsCollaboration

Tools & Technologies

SynopsysCadenceSiemensAMD/Xilinx VivadoIntel QuartusYosysOpenROADVerilatorCocotb

Industry Keywords

ASIC DesignFPGA DesignDigital Design FlowEngineering EvaluationAI Engineering Evaluations

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Develop realistic engineering evaluation tasks covering RTL design, functional verification, synthesis, physical design, and sign-off
Write reference implementations in Verilog, SystemVerilog, or VHDL, supported by testbenches, constraints, and expected results
Define clear grading criteria and validation methods reflecting industry-standard engineering expectations
Review AI-generated RTL, testbenches, hardware designs, and implementation results to identify functional errors and design weaknesses
Diagnose verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area decisions
Evaluate designs against functional correctness, timing constraints, resource utilisation, and implementation quality
Configure and maintain EDA-based environments enabling AI agents to execute realistic chip-design workflows
Work with Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, or Intel Quartus tools as relevant
Develop tasks assessing synthesis quality, place-and-route results, static timing analysis, and timing closure
Identify recurring AI-agent failure patterns and convert them into new evaluation scenarios and more challenging engineering tasks
Collaborate with engineering and research teams to improve evaluation environments, testing methods, and technical benchmarks
Automate design flows, testing, and result analysis using scripting languages
Document reference solutions, design assumptions, failure cases, and evaluation methodologies

Requirements

What you’ll need

3–5 years of hands-on ASIC or FPGA design experience, preferably across multiple stages of the digital design flow
B.E./B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline
Strong RTL development skills in Verilog, SystemVerilog, or VHDL
Practical experience with design verification, including testbench development, debugging, coverage analysis, and UVM or similar methodologies
Working knowledge of EDA tools and workflows from Synopsys, Cadence, Siemens, AMD/Xilinx, or Intel
Understanding of logic synthesis, place-and-route, static timing analysis, timing constraints, and timing closure
Sound engineering judgement when evaluating power, performance, and area (PPA) trade-offs
Experience taking at least one project from specification through implementation or tape-out
Strong debugging, analytical, and problem-solving skills, with the ability to explain precisely why a design succeeds or fails
Familiarity with Python, Tcl, or Perl for design-flow automation is an advantage
Exposure to open-source tools such as Yosys, OpenROAD, Verilator, or cocotb is beneficial
Interest in AI engineering evaluations, reinforcement-learning environments, or model post-training is a plus, but not required