Head of Memory Architecture

Xora Innovation

. Lead the architectural design of a purpose-built memory for AI inference computing .

Posted 10/13/2026full-timeSan Jose • California • United StatesLeadWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in memory architecture design and optimization for AI inference computing, with a strong focus on power, performance, area, and cost analysis. Proven ability to collaborate with cross-functional teams and leverage industry networks to drive innovative memory solutions.

Highest-signal resume keywords

Memory Architecture DesignPower, Performance, Area, Cost (PPAC) AnalysisAI Inference ComputingCollaboration with SoC ArchitectsIndustry Networking

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Memory Subsystem OptimizationMemory Vault DesignOn-Chip Interconnect DesignSense Amplifier DesignAddress TranslationBenchmarking AI Inference SoCsData-Center Workload AnalysisDevice Technology UnderstandingBit-Cell ArchitectureSilicon Area Analysis

Certifications & Qualifications

M.S. or Ph.D. in Computer ScienceM.S. or Ph.D. in Computer EngineeringM.S. or Ph.D. in Electrical Engineering

Industry Keywords

Agentic AI Inference ApplicationsLeading-Edge SoCsMemory IDMsMemory FootprintBandwidthLatencyPower EfficiencyDensityCost/BitNPI Teams

About the role

Key responsibilities & impact

Lead the architectural design of a purpose-built memory for AI inference computing
Design, model, and optimize memory subsystems for a new memory category and product
Balance memory footprint, bandwidth, latency, power efficiency, density, silicon area, and cost/bit
Design memory vaults and hierarchies, on-chip interconnects, sense amplifiers, and address translation
Analyze Agentic AI inference applications, software, AI inference models, and leading-edge SoCs for data-center workloads
Benchmark leading-edge AI inference SoC architectures and workload management against competing memory architectures and devices
Understand and leverage core materials and device technology for novel bit-cell and device architectures
Partner with SoC architects, NPI teams, silicon design, and technology teams to accelerate the product to market
Evangelize the memory offering and deepen understanding through industry and academia networks

Requirements

What you’ll need

M.S. or Ph.D. in Computer Science, Computer Engineering, or Electrical Engineering preferred
10+ years in memory architecture, preferably at leading memory IDMs
Deep grasp of state-of-the-art memory issues and challenges, particularly those associated with Agentic AI inference computing
Power, performance, area and cost (PPAC) analysis and modeling
Broad network of relevant industry and academia experts