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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in C++, Rust, and Python for formal verification and synthesis, with a solid understanding of RTL hardware design and model checking methodologies. Capable of developing and maintaining open-source EDA tools while supporting users and addressing challenges independently.
Highest-signal resume keywords
C++ ProgrammingRust ProgrammingFormal VerificationRTL Hardware DesignModel Checking
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
C++ ProgrammingRust ProgrammingPython ProgrammingFormal Verification ToolsHardware Model CheckingSynthesis FunctionalityRTL Hardware DesignAlgorithm ImplementationCompiler DevelopmentSAT/SMT Solving
Soft Skills
Independent WorkProblem SolvingUser SupportResponsibility
Tools & Technologies
Open-Source EDA ToolsYosysHQ Software Components
Industry Keywords
Formal MethodsAutomated Theorem ProvingInteractive Theorem ProvingProgramming Language TheoryAutomata TheoryASIC Design
Tech Stack
Tools & technologiesPythonRustC++
About the role
Key responsibilities & impact- Contribute to YosysHQ’s synthesis or formal verification focus areas
- Develop and maintain open-source EDA tools and software packages
- Work on formal verification tools using C++, Rust, and Python
- Implement hardware model checking and related formal methods
- Develop synthesis functionality using C++ and RTL hardware design knowledge
- Work on custom development of individual features and complete flows based on YosysHQ software components
- Support and train users and developers working with the software
- Independently take responsibility for assigned tasks and resolve challenges
- Participate in team meetings typically held between 3pm and 6pm Vienna time (CET/CEST)
Requirements
What you’ll need- Comfortable with C++ or Rust for formal verification; willingness to learn the other languages and Python
- Familiarity with implementation of hardware model checking, or background in verification/formal methods such as SAT/SMT solving, automated/interactive theorem proving, programming language theory, or automata theory
- Some contact with RTL hardware design for formal verification
- Comfortable with C++ for synthesis
- Some experience with RTL hardware design, ideally for ASIC
- Transferable experience building software for engineering or science applications, implementing algorithms from scientific literature, or working on a compiler
- Experience becoming familiar with a large pre-existing project
- Ability to take responsibility, work independently, and address challenges without extensive supervision
- Must not live in a country subject to sanctions or export restrictions, or be banned from performing work for the US government
- CV and brief cover letter required for application
Benefits
Comp & perks- Flexible remote work from wherever you are
- Flexible schedule; choose when to work outside team meetings
- Part-time option of 1–5 days per week
- Flat pay hierarchy with the same rate for everyone
- Opportunity to work on open-source EDA projects
- Work with synthesis and formal verification technologies
- Support and training for users and developers of software packages