Analog Layout Engineer

Arrow Components

. Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks .

Posted 10/24/2026full-timeAustin • Texas • United StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive experience in custom IC layout design, particularly for high-frequency mixed-signal circuits, with a strong focus on DRC, LVS, ERC compliance, and advanced CMOS/FinFET technologies. Proficient in creating block-level and chip-top-level floor plans while managing hierarchical block integration and addressing layout-dependent effects.

Highest-signal resume keywords

Custom IC Layout ExperienceAdvanced CMOS/FinFET NodesDRC, LVS, ERC ComplianceBlock-Level and Chip-Top-Level Floor PlansMicro-Bump or Package-Aware Co-Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Silicon Layout DesignHigh-Speed Mixed-Signal CircuitsDevice MatchingCommon-Centroid StructuresGuard RingsIsolation or ShieldingEM/IR ReliabilityESD ProtectionHierarchical Block IntegrationLayout-Dependent Effects

Certifications & Qualifications

Bachelor's Degree

Industry Keywords

SerDesADCsDACsPLLsDeep Sub-MicronTSMC N3TSMC N5TSMC N7Antenna RulesWPE

About the role

Key responsibilities & impact

Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks
Create block-level and chip-top-level floor plans
Manage hierarchical block integration
Handle micro-bump or package-aware co-design
Address layout-dependent effects, device matching, common-centroid structures, guard rings, and isolation or shielding
Ensure closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection

Requirements

What you’ll need

Generally 5 to 12+ years of hands-on custom IC layout experience
Experience in deep sub-micron or advanced CMOS/FinFET nodes, such as TSMC N3, N5, and N7
Experience at lower nodes (N3, N5) is critical
Bachelor’s degree
Ability to travel to an Arrow Client office location as requested by Arrow Client leadership
Experience with DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection
Knowledge of LOD, WPE, LDE, device matching, common-centroid structures, guard rings, and isolation or shielding
Experience creating block-level and chip-top-level floor plans, hierarchical block integration, and micro-bump or package-aware co-design

Benefits

Comp & perks

Remote work arrangement
Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company’s request and sole discretion