Physical Design Engineer II

Arrow Components

. Execute synthesis, PNR, and STA for assigned partitions of ASIC chips while adhering to strict schedules and design goals .

Posted 10/2/2026full-timeUnited StatesSeniorLead💰 $87,400 - $165,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in physical design and implementation, including synthesis, PnR, and physical verification, while adhering to strict schedules. Proficient in EDA tools and methodologies, with a strong focus on low-power design techniques and sub-7nm node technologies.

Highest-signal resume keywords

Physical Design ImplementationSynthesis and PnRElectronic Design Automation (EDA) ToolsSub-7nm Node TechnologiesTCL Scripting

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SynthesisPlace and Route (PnR)Timing ConvergencePhysical VerificationElectromigration and IR (EMIR)Power Delivery Network (PDN)Logical Equivalence Checking (LEC)System-on-Chip (SoC) DesignLow-Power Design TechniquesCustom Flows Development

Soft Skills

CollaborationProblem-SolvingAdherence to Schedules

Tools & Technologies

InnovusTempusQuantusCadence EDA ToolsSynopsys EDA Tools

Industry Keywords

Physical Design FlowsDesign MethodologiesElectronics EngineeringComputer EngineeringComputer Science

Tech Stack

Tools & technologies

Node.js

About the role

Key responsibilities & impact

Execute synthesis, PNR, and STA for assigned partitions of ASIC chips while adhering to strict schedules and design goals
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across blocks
Help close EM/IR, drive LEC, and complete physical verification signoff for assigned partitions in coordination with methodology owners
Partner with the design team to identify and address potential physical design challenges, enabling efficient iteration and convergence
Contribute to refining implementation and physical design methodologies, including synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC)
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed

Requirements

What you’ll need

Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification
Proficiency in Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus
Deep understanding of physical design flows and methodologies
7+ years of experience in physical design roles and related activities
Proven ability to adhere to tight schedules and implement low-power design techniques
Experience in System-on-Chip (SoC) design and implementation
Expertise in sub-7nm node technologies
Familiarity with industry-standard EDA tools and their capabilities
Strong scripting skills in TCL
Ability to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys
Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership

Benefits

Comp & perks

Medical, Dental, Vision Insurance
401k, With Matching Contributions
Short-Term/Long-Term Disability Insurance
Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
Paid Time Off (including sick, holiday, vacation, etc.)
Tuition Reimbursement
Growth Opportunities
Competitive financial compensation
Various compensation plans
Solid benefits package