Physical Design Engineer II

Arrow Components

. Perform RTL to Physical Design (RTL2PD) activities for ASICs .

Posted 10/28/2026full-timeUnited StatesSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates extensive expertise in RTL Synthesis, RTL to Physical Design (RTL2PD), and Static Timing Analysis (STA), with a strong ability to write constraints, debug synthesis issues, and generate clean netlists. Proficient in scripting for RTL synthesis and EDA tools, with experience in multi-node designs.

Highest-signal resume keywords

RTL SynthesisRTL To Physical Design (RTL2PD)Static Timing Analysis (STA)EDA Tools: Design Compiler, PrimeTime, Tempus, Genus, InnovusMulti-Node Design Experience

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

RTL SynthesisRTL To Physical Design (RTL2PD)Static Timing Analysis (STA)Constraint WritingDebugging Synthesis IssuesGenerating Clean NetlistsScripting for RTL SynthesisSDC CreationValidationMulti-Node Design Experience

Tools & Technologies

Design CompilerPrimeTimeTempusGenusInnovus

Industry Keywords

ASICElectronic EngineeringEDANetlistClient Interaction

Tech Stack

Tools & technologies

Node.js

About the role

Key responsibilities & impact

Perform RTL to Physical Design (RTL2PD) activities for ASICs
Perform RTL synthesis
Write constraints and validate them
Conduct Static Timing Analysis (STA)
Write or modify scripts for RTL synthesis, SDC creation, and STA
Debug synthesis issues and STA
Generate clean netlists
Work on multi-node designs
Travel to and work at Arrow client office locations as requested
Complete work on-site in San Jose, California or Austin, Texas

Requirements

What you’ll need

8–12 years of hands-on RTL Synthesis experience
Experience with RTL to Physical Design (RTL2PD) stage
Experience with RTL Synthesis, constraint writing, validation, and Static Timing Analysis
Experience writing or modifying scripts for RTL synthesis, SDC creation, and STA
Experience debugging synthesis issues and STA
Experience generating clean netlists
EDA exposure to Design Compiler, PrimeTime, Tempus, Genus, and Innovus
Experience working with 16nm, 7nm, and other multi-node designs
Bachelor’s Degree in electronic engineering, or the equivalent qualification in training and experience
Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership

Benefits

Comp & perks

Competitive financial compensation
Medical, Dental, Vision Insurance
401k, With Matching Contributions
Short-Term/Long-Term Disability Insurance
Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
Paid Time Off (including sick, holiday, vacation, etc.)
Tuition Reimbursement
Growth Opportunities