FPGA Developer

AscendArc

. Architect, write, and verify synthesizable RTL in SystemVerilog or VHDL for modern FPGAs .

Posted 11/10/2026full-timeRemote • Oregon • United StatesSeniorLead💰 $180,000 - $230,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in FPGA development using SystemVerilog and VHDL, with a strong foundation in DSP and signal processing. Proficient in integrating IP cores, developing simulation testbenches, and driving hardware bring-up in high-reliability environments.

Highest-signal resume keywords

FPGA DevelopmentSystemVerilogVHDLDSP FundamentalsVivado Toolchain

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignModulation and DemodulationPacket-SwitchingFIR FiltersCIC FiltersNCOsSimulation TestbenchesSynthesisTiming ClosureUtilization Analysis

Soft Skills

CollaborationTechnical Direction Influence

Tools & Technologies

UVMCocotbGitVivadoADC/DAC Interfaces

Industry Keywords

High-Reliability EnvironmentsRadiation-Tolerant DesignTMRSEU MitigationAXI/AXI-StreamClock-Domain Crossing

Tech Stack

Tools & technologies

DACSwitching

About the role

Key responsibilities & impact

Architect, write, and verify synthesizable RTL in SystemVerilog or VHDL for modern FPGAs
Integrate and configure modulation, demodulation, and packet-switching/routing IP cores
Implement DSP blocks including FIR/CIC/polyphase filters, NCOs, mixers, decimation/interpolation chains, channelizers, and demodulation/synchronization logic
Develop simulation testbenches using UVM, cocotb, or similar tools
Drive functional and code coverage and own hardware bring-up
Take designs through synthesis, place-and-route, and timing closure
Analyze utilization, congestion, and Fmax issues and resolve them at the RTL level
Integrate ADC/DAC front-ends and mixed-signal interfaces, including clocking, calibration, and lane alignment
Collaborate with systems, firmware, and hardware engineers on interface definitions and hardware/software partitioning
Produce design documentation, interface control documents, and verification reports
Influence technical direction and help shape communications architecture for next-generation spacecraft

Requirements

What you’ll need

B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience
8+ years of professional FPGA development in SystemVerilog and/or VHDL
Experience integrating third-party or vendor IP cores into larger FPGA designs
Understanding of packet-based routing and switching concepts, including arbitration, buffering, backpressure, and link-layer framing
Strong DSP fundamentals and hands-on fixed-point HDL signal-processing experience
Experience with high-speed serial transceivers, including 8b/10b or 64b/66b encoding, comma alignment, and lane bonding
Proficiency with the full Vivado toolchain: synthesis, implementation, timing analysis, and XDC/SDC constraint authoring
Strong verification skills, including self-checking testbenches, constrained-random stimulus, and coverage-driven methodology
Comfort with Git-based workflows and code review
Preferred: RF and analog front-end experience
Preferred: JESD204B/C high-speed converter-interface experience
Preferred: Space, defense, or other high-reliability-environment experience, including radiation-tolerant design practices, TMR, scrubbing, and SEU mitigation
Preferred: AXI/AXI-Stream interconnect and DMA architecture familiarity
Preferred: Clock-domain crossing methodology, formal CDC verification, and hardware bring-up with lab instrumentation