Application Engineer, Architect – STA SignOff

Cadence Design Systems

. Lead technical engagements with customers and partners to drive adoption of Cadence signoff portfolio .

Posted 10/15/2026full-timeUnited StatesSeniorLead💰 $154,000 - $286,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates extensive expertise in IC design implementation and signoff, with a strong focus on advanced node STA, timing signoff methodologies, and customer engagement. Proven ability to lead technical teams and drive customer success through effective communication and negotiation.

Highest-signal resume keywords

IC Design ImplementationTiming Signoff ExpertiseAdvanced Node STAScripting Proficiency (Tcl, Python, Perl)Leadership in Technical Programs

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Digital Design FundamentalsCore Timing SignoffFlow Customization for Design ClosureUPF & Constraints DebuggingHierarchical & 3DIC Design STAECOs (3nm and Below)Complex BenchmarkingFlow OptimizationPower/Timing ClosureCustomer Success Metrics

Soft Skills

Excellent CommunicationNegotiation SkillsLeadership Skills

Tools & Technologies

Cadence Tools (Tempus, Certus, QRC)EDA Tool Ecosystems

Certifications & Qualifications

BS/MS in Electrical EngineeringComputer Engineering

Industry Keywords

Technical EngagementsCustomer SuccessMarket LeadershipTechnical PapersKeynote Presentations

Tech Stack

Tools & technologies

Node.jsPerlPython

About the role

Key responsibilities & impact

Lead technical engagements with customers and partners to drive adoption of Cadence signoff portfolio
Work closely with design teams to meet customer success metrics
Guide adoption of Cadence’s timing signoff, closure, and AgenticAI features across advanced nodes (5nm and below)
Partner with R&D and Product Engineering to influence tool enhancements based on customer requirements
Drive complex benchmarks, flow optimizations, and deployment of methodologies for timing signoff and closure, STA, IR Drop, and power/timing closure
Represent Cadence at industry forums
Author technical papers
Deliver keynote presentations to position Cadence as a market leader

Requirements

What you’ll need

15+ years of experience in IC design implementation and signoff
Demonstrated success in managing large-scale technical programs
BS/MS in Electrical Engineering, Computer Engineering, or related field
Deep expertise in digital design fundamentals
Advanced node STA & ECOs (3nm and below)
EDA tool ecosystems
Core timing signoff expertise
Advanced node STA
UPF & constraints debugging
Hierarchical & 3DIC design STA and closure solutions
Proven track record of leading technical teams and driving customer success at executive levels
Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure
Excellent communication, negotiation, and leadership skills
Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable

Benefits

Comp & perks

Incentive compensation: bonus
Equity
Paid vacation
Paid holidays
401(k) plan with employer match
Employee stock purchase plan
Medical plan options
Dental plan options
Vision plan options