Cadence Design Systems

Mechanical Engineer

• Develop extremely high-speed wireline communications transceivers in CMOS silicon
• Perform numerical modeling and architecture work for transceiver components using mathematical and computer modeling techniques
• Guide selection and specification of transceiver components
• Collaborate with analog designers, digital designers, applications engineers, and marketing specialists
• Guide tradeoffs among conflicting design goals
• Take responsibility for end-to-end system performance
• Participate in laboratory characterization and analysis of realized designs

Principal Design Engineer

Full-stack Engineer

• Work as a Product Engineer supporting Conformal products
• Focus on customer success as part of an engineering team
• Work closely with R&D to deliver new product features, enhancements, and solutions
• Become an expert in Conformal products, especially equivalency checking (Conformal LEC)
• Represent R&D in front of customers and represent customers in front of R&D
• Provide regular updates
• Troubleshoot ambiguous problem statements
• Narrow down root causes and discover acceptable workarounds
• Translate issues for R&D to fix
• Provide systematic debugging and educated decision making under strict deadlines

Product Engineer II, Conformal

Architect

• Lead and run the Processor Verification team
• Verify microprocessor cores and their peripherals
• Craft verification plans and execute them for highly complex CPU designs
• Implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers, or coverage monitors
• Collect and close coverage
• Work closely with DV, Architecture, Design, and Firmware cross-functional teams to identify coverage scope
• Track and report the work of 7–10 engineers

Design Verification Architect – Director

AI Engineer

• Build ETL/ELT pipelines that extract data from source code, APIs, file formats, and documentation and load it into a structured knowledge store
• Design and maintain schemas and semantic data models capturing entities, relationships, and capabilities
• Construct and maintain knowledge graphs over heterogeneous product data
• Develop source and metadata parsers, including source-code/AST parsing, to extract structure automatically
• Build typed programmatic interfaces and data-access layers over the knowledge layer
• Implement retrieval and indexing layers, including embeddings and RAG, over product knowledge
• Work with domain engineers to decompose complex product workflows into discrete, callable operations
• Assess data sources for coverage, quality, and schema completeness across multiple products
• Build structured knowledge and interfaces over product capabilities across multiple products
• Collaborate closely with domain engineers who provide subject-matter expertise

AI Engineer, Ontologies, Knowledge Graphs

• Assist in running and monitoring Logical Equivalence Checking (LEC), Logic Synthesis, and Conformal Low Power jobs across design blocks
• Support constraint reviews, generation, and basic debugging
• Track and document LEC and synthesis status across blocks
• Learn and apply power intent basics to support CLP sign-off tasks
• Support ECO script writing and basic scripting tasks using Tcl, Perl, or Python
• Maintain documentation of runs, issues, and findings
• Support execution-level tasks across the ASIC design flow

Design Engineer I – Synthesis, LEC, CLP

• Run and debug LEC sign-off on design blocks
• Investigate and resolve NEQs and constraint mismatches
• Work on Genus synthesis runs to improve QoR
• Debug SDC and constraint issues
• Support CLP flows
• Write and maintain ECO scripts and timing/power constraints for design blocks
• Independently triage and document issues, escalating complex or systemic issues as needed
• Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis, LEC, and CLP closure
• Prepare status updates and technical summaries for internal tracking
• Execute Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs

Lead Design Engineer – Synthesis, LEC, CLP

• Drive methodology improvements and best-practice development across Synthesis, LEC, CLP, and ECO flows
• Own end-to-end LEC sign-off across multiple design blocks
• Debug NEQs and aborts
• Drive physical synthesis closure on complex blocks
• Develop constraints and achieve PPA closure
• Lead CLP sign-off for low-power intent designs
• Resolve level shifter, retention, isolation, PSO strategy architecture, and supply set/domain conflicts
• Own technical documentation, status tracking, and write-ups across active blocks
• Contribute to flow methodology and root-cause resolution for synthesis, LEC, and low-power sign-off