Lead Design Engineer – Synthesis, LEC, CLP

Cadence Design Systems

. Run and debug LEC sign-off on design blocks .

Posted 9/15/2026full-timeBangalore • IndiaSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ASIC synthesis, LEC, and low-power verification flows, with strong scripting skills in Tcl, Perl, or Python. Proficient in collaborating across teams to resolve complex design issues while maintaining effective communication and documentation.

Highest-signal resume keywords

ASIC SynthesisLEC (Logic Equivalence Checking)Low-Power VerificationCadence GenusScripting Proficiency in Tcl, Perl, or Python

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC SynthesisLECLow-Power VerificationScripting in TclScripting in PerlScripting in PythonDigital Design FundamentalsSTA BasicsPower Intent (UPF/CPF)Debugging SDC and Constraint Issues

Soft Skills

Strong Communication SkillsAbility to Work Independently

Tools & Technologies

Cadence GenusConformalUnix/Linux

Certifications & Qualifications

BE/BTech/ME/MS/MTech in Electrical/Electronic

Industry Keywords

QoR (Quality of Results)ECO ScriptsTiming ConstraintsPower ConstraintsCLP FlowsNEQs (Not Equivalent)

Tech Stack

Tools & technologies

LinuxPerlPythonUnix

About the role

Key responsibilities & impact

Run and debug LEC sign-off on design blocks
Investigate and resolve NEQs and constraint mismatches
Work on Genus synthesis runs to improve QoR
Debug SDC and constraint issues
Support CLP flows
Write and maintain ECO scripts and timing/power constraints for design blocks
Independently triage and document issues, escalating complex or systemic issues as needed
Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis, LEC, and CLP closure
Prepare status updates and technical summaries for internal tracking
Execute Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs

Requirements

What you’ll need

5–8 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows
BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent
Working knowledge of Cadence Genus and Conformal (LEC and/or CLP)
Familiarity with UPF/CPF-based power intent (IEEE 1801)
Scripting proficiency in Tcl, Perl, or Python
Comfortable working in Unix/Linux-based environments
Solid understanding of digital design fundamentals, STA basics, and low-power architecture concepts
Strong communication skills and ability to work independently on assigned blocks

Benefits

Comp & perks

Employee-friendly policies focused on physical and mental well-being
Career development opportunities
Learning and development opportunities
Diverse, collaborative team environment
Recognition and celebration of employee success
Opportunities to work on cutting-edge technology