Principal Design Engineer

Cadence Design Systems

. Implement and verify Palladium and Protium SOCs through timing closure to tape out .

Posted 10/9/2026full-timeSan Jose • California • United StatesLead💰 $140,000 - $260,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in implementing and verifying SOCs, including timing closure and physical verification, while leading teams and interfacing with design and verification teams. Proficient in using advanced technologies and industry-standard tools for efficient chip design and optimization.

Highest-signal resume keywords

SOC ImplementationRTL SynthesisCadence Tools ExperienceScript DevelopmentAdvanced Technology Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL SynthesisTiming ClosurePhysical VerificationClock Tree OptimizationScript DevelopmentLinux Server UsageDesign DocumentationFloor PlanningIR Drop AnalysisTeam Leadership

Tools & Technologies

Cadence InnovusCadence TempusCadence QRCCadence VoltusCadence Pegasus

Industry Keywords

5nm Technology3nm Technology2nm TechnologyPCI ExpressDDRLPDDRSRAMUCIe

Tech Stack

Tools & technologies

LinuxPerl

About the role

Key responsibilities & impact

Implement and verify Palladium and Protium SOCs through timing closure to tape out
Lead a team to implement SOCs or subsystem chips
Perform RTL synthesis and floor planning
Build clock trees and perform optimizations
Close timing, IR drop and physical verification
Review and document designs for tape-out
Interface with front-end RTL design teams and back-end verification teams

Requirements

What you’ll need

BS in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum of 1 year of experience
Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
Experience with advanced technologies like 5nm, 3nm and 2nm nodes
Experience using Linux servers
Script development using Shell, Perl and TCL
Detailed knowledge of industry-standard interfaces such as PCI Express, DDR, LPDDR, SRAM and UCIe

Benefits

Comp & perks

Paid vacation
Paid holidays
401(k) plan with employer match
Employee stock purchase plan
Medical, dental and vision plan options
Incentive compensation: bonus and equity
Opportunities for learning and development
Career development opportunities
Employee well-being programs
Diverse and collaborative team environment