FREE ACCESS
5,000–10,000 jobs/day
See all jobs on Scoutfield
Search thousands of fresh jobs every day.
Discover
- Fresh listings
- Fast filters
- No subscription required
Create a free account and start exploring right away.

Principal Design Engineer – Synthesis, LEC, CLP
Cadence Design Systems. Drive methodology improvements and best-practice development across Synthesis, LEC, CLP, and ECO flows .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates extensive expertise in ASIC/SoC design, with a strong focus on Synthesis, LEC, and Low Power methodologies. Proficient in technical documentation and cross-team collaboration to drive project success.
Highest-signal resume keywords
ASIC/SoC Design ExperienceSynthesis Using GenusLEC Using ConformalLow Power DesignScripting Ability in TCL, Python, PERL
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
SynthesisLECLow PowerMulti-Corner Sign-OffMulti-Mode Sign-OffDebugging NEQsPPA ClosureConstraints DevelopmentRoot-Cause ResolutionPhysical Design Handoff
Soft Skills
Excellent Written CommunicationExcellent Verbal CommunicationCross-Team Collaboration
Certifications & Qualifications
BE/BTech/ME/MS/MTech in Electrical/Electronic
Industry Keywords
Synthesis MethodologyLEC MethodologyTechnical DocumentationFast-Paced EnvironmentFlow Methodology
Tech Stack
Tools & technologiesPerlPython
About the role
Key responsibilities & impact- Drive methodology improvements and best-practice development across Synthesis, LEC, CLP, and ECO flows
- Own end-to-end LEC sign-off across multiple design blocks
- Debug NEQs and aborts
- Drive physical synthesis closure on complex blocks
- Develop constraints and achieve PPA closure
- Lead CLP sign-off for low-power intent designs
- Resolve level shifter, retention, isolation, PSO strategy architecture, and supply set/domain conflicts
- Own technical documentation, status tracking, and write-ups across active blocks
- Contribute to flow methodology and root-cause resolution for synthesis, LEC, and low-power sign-off
Requirements
What you’ll need- 8–12 years of hands-on ASIC/SoC design experience
- BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent
- Strong depth in Synthesis using Genus
- Strong depth in LEC using Conformal
- Strong depth in Low Power
- Experience with multi-corner, multi-mode sign-off considerations
- Strong scripting ability in TCL, Python, PERL, etc.
- Deep understanding of ASIC flow interactions: RTL, synthesis, physical design handoff, and DFT
- Excellent written and verbal communication skills
- Comfortable owning technical documentation and cross-team discussions
- Proven track record of working in a fast-paced environment
Benefits
Comp & perks- Employee-friendly policies focused on physical and mental well-being
- Career development opportunities
- Learning and development opportunities
- Recognition and celebration of employee success
- Collaborative One Cadence – One Team culture
- Opportunity to work with diverse teams
- Cutting-edge technology and creative, innovative work environment