FREE ACCESS
5,000–10,000 jobs/day
See all jobs on Scoutfield
Search thousands of fresh jobs every day.
Discover
- Fresh listings
- Fast filters
- No subscription required
Create a free account and start exploring right away.
Product Engineer II, Memory IP
Cadence Design Systems. Support pre-silicon integration, usage, and implementation of memory subsystem products .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in memory subsystem integration, including RTL design, gate-level verification, and timing analysis. Proficient in collaborating with customers and cross-functional teams to enhance product functionality and customer experience.
Highest-signal resume keywords
RTL DesignGate-Level VerificationStatic Timing AnalysisDDR5/4/3 ExperienceMemory PHY Integration
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
VerilogSynthesisStatic Timing AnalysisDFT FlowsTest MethodologiesPackage DesignBoard DesignSI/PI ReviewsEmbedded Microcontroller FirmwareDSP-Based Architecture
Soft Skills
Customer SupportCollaborationProblem SolvingCommunicationTime Management
Tools & Technologies
AI-Powered ToolsAI-Powered Analytics
Industry Keywords
Memory SubsystemControllerPHYPre-Silicon IntegrationPost-Silicon Bring-UpQA TestingPhysical IntegrationTiming ClosureProduct DocumentationRemote Team Collaboration
About the role
Key responsibilities & impact- Support pre-silicon integration, usage, and implementation of memory subsystem products
- Help with internal system integration and QA testing of memory subsystem products (Controller + PHY)
- Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers
- Support memory PHY and controller SoC integration reviews and implementation reviews
- Assist customers with RTL and gate-level simulations to verify functionality
- Assist customers with timing closure and other aspects of physical integration
- Participate in development and refinement of product documentation and checklists for customer applications
- Support post-silicon bring-up and production test activities for customers as needed
- Enhance customer experience by providing prompt, thorough, and technically accurate responses to customer questions
- Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables
- Apply AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets
- Act as a primary interface between customers, Cadence R&D, and System Validation teams
- Collaborate with remote teams located worldwide and manage multiple priorities
Requirements
What you’ll need- B.S. Electrical/Computer Engineering (or similar degree) with minimum 2 years of relevant industry experience OR M.S. Electrical/Computer Engineering (or similar degree)
- Experience working with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar IPs
- Verilog RTL design and gate-level verification experience
- Synthesis and static timing analysis experience
- Familiarity with industry-standard DFT flows and test methodologies
- Familiarity with package and board design
- Ability to read schematics and participate in SI/PI reviews for customer board/package implementation
- Preferred: M.S. Electrical/Computer Engineering (or similar degree) with 2+ years of relevant industry experience
- Preferred: Experience with Memory PHY and DSP-based architecture
- Preferred: Experience with embedded microcontroller firmware
Benefits
Comp & perks- Opportunity to work with an experienced team and top technology-sector companies
- Opportunity to work on high-performance Memory PHY IP products
- Opportunity to leverage AI-powered tools and assistants to enhance productivity and decision making