STA Application Engineer

Cadence Design Systems

. Perform static timing analysis, glitch analysis, and noise analysis using the Tempus Signoff tool .

Posted 11/6/2026full-timeUnited StatesMid-LevelSenior💰 $106,400 - $197,600 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in static timing analysis, glitch analysis, and noise analysis using the Tempus Signoff tool, along with proficiency in scripting languages such as Perl, Tcl, and Python for automation. Capable of delivering technical trainings and collaborating with R&D and customers on advanced timing analysis methodologies.

Highest-signal resume keywords

Static Timing AnalysisTempus Signoff ToolECO FlowsScripting Proficiency in Perl, Tcl, PythonTiming Correlation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Static Timing AnalysisGlitch AnalysisNoise AnalysisTiming Analysis FlowsECO FlowsSDC ConstraintsAdvanced OCV/SOCV ConceptsTiming CorrelationSpice AnalysisIn-Design Timing ECO Optimization

Soft Skills

CollaborationTechnical Training Delivery

Tools & Technologies

Tempus Signoff ToolCAD ToolsPerlTclPython

Industry Keywords

PBA TimingDistributed STA FlowsConcurrent STA FlowsPlace and RouteClock TreeRC ExtractionUPF/CPF Concepts

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Perform static timing analysis, glitch analysis, and noise analysis using the Tempus Signoff tool
Execute and deliver timing analysis flows, ECO flows, CAD tools, and methodologies
Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, and Distributed and Concurrent STA flows
Collaborate with R&D and customers to enable timing analysis and ECO flows, including newer advanced technologies
Perform timing correlation, tool feature benchmarking, constraints validation, and spice analysis across technology nodes and customer designs
Develop in-design timing ECO optimization solutions
Execute and lead Tempus timing signoff campaigns at existing and new customers
Automate flows using Perl, Tcl, and Python
Deliver technical trainings and seminars within Cadence and at customer sites

Requirements

What you’ll need

Experience performing static timing analysis, glitch analysis, and noise analysis using Tempus Signoff tool
Experience with timing analysis flows, ECO flows, CAD tools, and methodologies
Knowledge of SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, and Distributed and Concurrent STA flows
Ability to work with R&D and customers on timing analysis and ECO flows
Experience with timing correlation, tool feature benchmarking, constraints validation, and spice analysis
Basic knowledge of Place and Route, Clock Tree, RC Extraction, and UPF/CPF concepts
Experience executing and leading Tempus timing signoff campaigns
Scripting proficiency in Perl, Tcl, or Python
Ability to deliver technical trainings and seminars
Relevant qualifications, skills, competencies, and work-location requirements for compensation consideration

Benefits

Comp & perks

Incentive compensation: bonus
Incentive compensation: equity
Paid vacation
Paid holidays
401(k) plan with employer match
Employee stock purchase plan
Medical, dental and vision plan options