Graduate Digital Design Engineer

Ceva, Inc.

. Write and debug RTL (Verilog/SystemVerilog) for blocks within 5G baseband DSP cores and hardware accelerators under senior engineers' guidance .

Posted 11/9/2026full-timeRa'anana • IsraelEntry LevelWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in RTL design using Verilog or SystemVerilog, with a solid understanding of digital design fundamentals and experience in simulation and EDA tools. Capable of collaborating effectively with cross-functional teams to integrate designs into complex systems.

Highest-signal resume keywords

RTL Design in VerilogDigital Design FundamentalsSimulation and EDA ToolsProblem-Solving SkillsClear Communication in English

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignVerilogSystemVerilogDigital DesignLogic DesignFinite State Machines (FSMs)PipeliningClockingTiming AnalysisScripting (Python, Tcl, Perl)

Soft Skills

Eagerness to LearnGood Problem-Solving SkillsClear Communication

Tools & Technologies

SynopsysCadenceSiemens EDAMentor Graphics

Certifications & Qualifications

B.Sc. in Electrical EngineeringM.Sc. in Electrical Engineering

Industry Keywords

VLSI Design5G Baseband DSPDigital Communication SystemsSignal Processing

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Write and debug RTL (Verilog/SystemVerilog) for blocks within 5G baseband DSP cores and hardware accelerators under senior engineers' guidance
Translate block-level specifications into clean, well-documented, synthesizable designs
Run lint, synthesis and timing analysis on blocks and help resolve resulting issues
Support verification engineers with testbench bring-up, failure debugging and coverage goals
Participate in design reviews and learn to evaluate power, performance and area trade-offs
Collaborate with algorithm, verification and backend teams to understand blocks' integration into the full modem

Requirements

What you’ll need

B.Sc. in Electrical or Computer Engineering (recent graduates)
Experience in digital or VLSI design from student projects or internships
Solid grasp of digital design fundamentals: logic design, FSMs, pipelining, clocking and timing
Basic familiarity with simulation and EDA tools (Synopsys, Cadence, Siemens EDA/Mentor or similar)
Eagerness to learn, good problem-solving skills and clear communication in English
Hands-on RTL design in Verilog or SystemVerilog, from academic or industry projects (advantage)
M.Sc. in Electrical Engineering (advantage)
Coursework or projects in signal processing or digital communication systems (advantage)
Scripting skills (Python, Tcl or Perl) for design automation (advantage)

Benefits

Comp & perks

Hands-on role with close collaboration across algorithms, architecture, verification and backend teams
Strong place to build a career in VLSI design