Ceva, Inc.

Engineer

• Develop and maintain SystemVerilog/UVM verification environments from scratch, including constrained-random tests, reusable UVM components, assertions and functional coverage
• Integrate multiple verification environments and verification IPs into larger subsystem and system-level environments
• Define verification plans and test scenarios, and verify Bluetooth/BLE and IEEE 802.15.4 features, protocol behavior, corner cases and error conditions
• Debug complex RTL and testbench issues and drive verification activities from planning and environment development through coverage closure
• Drive technical topics autonomously with limited supervision while collaborating closely with verification engineers, RTL designers, architects and other cross-functional teams
• Support the integration team with integrating the Bluetooth verification environment into larger connectivity environments

Senior Verification Engineer – WIOT