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Senior Verification Engineer – WIOT
Ceva, Inc.. Develop and maintain SystemVerilog/UVM verification environments from scratch, including constrained-random tests, reusable UVM components, assertions and functional coverage .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates extensive experience in ASIC/SoC verification, with a strong focus on developing and maintaining SystemVerilog/UVM verification environments. Proficient in debugging complex RTL issues and integrating Bluetooth/BLE and IEEE 802.15.4 standards into verification processes.
Highest-signal resume keywords
SystemVerilogUVMBluetooth/Bluetooth Low Energy (BLE)IEEE 802.15.4ASIC/SoC Verification
ATS Keywords
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Hard Skills
SystemVerilog Assertions (SVA)Verification Environment DevelopmentDebuggingProblem-SolvingFormal VerificationScripting (Python)Verification Plan DefinitionFunctional CoverageConstrained-Random TestingRTL Understanding
Soft Skills
CollaborationCommunicationTechnical OwnershipAutonomy
Industry Keywords
Wireless Protocol VerificationSubsystem VerificationSoC-Level VerificationVerification IP Integration
Tech Stack
Tools & technologiesPython
About the role
Key responsibilities & impact- Develop and maintain SystemVerilog/UVM verification environments from scratch, including constrained-random tests, reusable UVM components, assertions and functional coverage
- Integrate multiple verification environments and verification IPs into larger subsystem and system-level environments
- Define verification plans and test scenarios, and verify Bluetooth/BLE and IEEE 802.15.4 features, protocol behavior, corner cases and error conditions
- Debug complex RTL and testbench issues and drive verification activities from planning and environment development through coverage closure
- Drive technical topics autonomously with limited supervision while collaborating closely with verification engineers, RTL designers, architects and other cross-functional teams
- Support the integration team with integrating the Bluetooth verification environment into larger connectivity environments
Requirements
What you’ll need- 7+ years of ASIC/SoC verification experience
- Strong SystemVerilog, UVM and SystemVerilog Assertions (SVA) knowledge, with proven experience building UVM verification environments from scratch
- Experience integrating multiple verification environments, with a good understanding of RTL and digital design
- Strong debugging and problem-solving skills
- High level of autonomy, technical ownership, collaboration and communication skills across teams and departments
- Fluent English
- Knowledge of Bluetooth / Bluetooth Low Energy (BLE) and IEEE 802.15.4 standards
- Wireless protocol and IP verification experience, including subsystem or SoC-level verification
- Python or other scripting language experience
- Formal verification experience
Benefits
Comp & perks- No benefits, perks, or compensation extras are specified