Senior VLSI Design Engineer

Ceva, Inc.

. Design and implement high-performance 5G baseband DSP cores and hardware accelerators for transmit and receive chains .

Posted 10/21/2026full-timeRa'anana • IsraelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in VLSI design, RTL development, and digital communication systems, with a strong focus on optimizing power, performance, and area in high-performance 5G baseband DSP cores. Proven ability to collaborate with cross-functional teams throughout the design flow from architecture to silicon bring-up.

Highest-signal resume keywords

VLSI DesignRTL Design (Verilog/SystemVerilog)EDA Tools (Synopsys, Cadence, Siemens EDA/Mentor)Digital Design PrinciplesSignal Processing

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignSynthesisTiming AnalysisDigital Design PrinciplesSoC ArchitectureLow-Power TechniquesCDC/RDC AnalysisDFTMulti-Power-Domain DesignLicensable IP Delivery

Soft Skills

Problem-SolvingCommunication

Certifications & Qualifications

B.Sc./M.Sc. in Electrical Engineering

Industry Keywords

5GBaseband DSPHardware AcceleratorsMulti-Antenna SystemsSatellite Connectivity

About the role

Key responsibilities & impact

Design and implement high-performance 5G baseband DSP cores and hardware accelerators for transmit and receive chains
Develop programmable DSP architectures for multi-antenna systems, including satellite connectivity
Own the design flow from architecture and RTL development through verification support, synthesis, and timing closure
Optimize power, performance, and area (PPA) in collaboration with backend and cross-functional teams
Work closely with algorithm, verification, backend, and software teams, as well as customers, from specification to silicon bring-up

Requirements

What you’ll need

B.Sc./M.Sc. in Electrical Engineering
5–10 years of experience in VLSI design
Proficiency in RTL design (Verilog/SystemVerilog), synthesis and timing analysis
Familiarity with EDA tools (Synopsys, Cadence, Siemens EDA/Mentor)
Strong understanding of digital design principles, SoC architecture and low-power techniques
Excellent problem-solving and communication skills
Knowledge of signal processing and digital communication systems is an advantage
Experience with CDC/RDC analysis, DFT and multi-power-domain design is an advantage
Experience delivering licensable IP to external customers is an advantage

Benefits

Comp & perks

No benefits or compensation extras specified