ASIC Design Hardware Engineer – SDC/STA

Cisco

. Develop block-level and full-chip SDCs .

Posted 9/23/2026full-timeSan Jose • California • United StatesJuniorMid-Level💰 $155,000 - $222,600 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in developing and validating block-level and full-chip SDCs, utilizing tools such as TCM and Timevision, while ensuring timing correctness and quality throughout the design cycle. Proficient in digital design concepts, including clocking structures and RTL implementation, with strong collaboration skills across technical teams.

Highest-signal resume keywords

Block-Level And Full-Chip SDC DevelopmentTiming Constraint ValidationTCL ScriptingDigital Design ConceptsCross-Functional Collaboration

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SDC DevelopmentTiming ConstraintsVerilog/SystemVerilog ProgrammingShell ScriptingPerl ScriptingSynthesis ToolsSTA ToolsDigital Design ConceptsMicroarchitectureRTL Implementation

Soft Skills

Problem-SolvingTechnical CommunicationEffective Documentation

Tools & Technologies

TCMTimevisionSynopsys DC/DCG/FCPrimeTime

Industry Keywords

ASICClocking StructuresTiming ExceptionsAsynchronous BoundariesFull-Chip Timing Closure

Tech Stack

Tools & technologies

Perl

About the role

Key responsibilities & impact

Develop block-level and full-chip SDCs
Work with physical design and DFT teams to close full-chip timing across multiple timing modes
Understand clocking structures with design and architecture teams
Develop timing constraints and validate them with constraint verification tools before physical design release
Identify and resolve timing issues across design levels
Develop and validate timing constraints using tools such as TCM and Timevision
Collaborate with front-end and back-end teams to refine design and timing constraints for physical design closure
Perform optional block-level RTL design or block- or top-level IP integration
Develop methodologies to promote block-level SDCs to full-chip and push down full-chip SDCs to block level
Develop and apply methodologies to ensure SDC correctness and quality early in the design cycle
Review block-level SDCs and clocking diagrams with RTL design owners
Contribute to full-chip clocking design, diagrams, and documentation
Contribute to next-generation networking chip development

Requirements

What you’ll need

Bachelor’s Degree in Electrical or Computer Engineering with 4+ years of ASIC or related experience, or Master’s Degree in Electrical or Computer Engineering with 2+ years of ASIC or related experience
Experience with synthesis tools such as Synopsys DC/DCG/FC
Experience with STA tools such as PrimeTime
Knowledge of HDL, including Verilog/SystemVerilog programming
Experience with Shell and Perl scripting
Strong TCL scripting experience
Experience with digital design concepts, including clocking, timing exceptions, and asynchronous boundaries
Experience with block/full-chip SDC development in functional and test modes
Experience with microarchitecture and RTL implementation
Effective documentation, problem-solving, and technical communication skills
Experience working cross-functionally with technical teams
Must live within commuting distance of the San Jose, CA office and commute 4–5 days per week

Benefits

Comp & perks

Onsite gym, healthcare, and café
Social interest groups and philanthropy opportunities
Medical, dental, and vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Potential Cisco restricted stock unit grants
10 paid holidays plus 1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid personal wellness days
16 days of paid vacation per calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire and annually, with up to 80 unused hours carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per year
Annual bonuses for non-sales roles
Global growth and development opportunities