ASIC Design Verification Engineer I

Cisco

. Maintain and enhance existing design verification environments .

Posted 10/26/2026full-timeUnited StatesMid-LevelSenior💰 $107,800 - $157,400 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC Design and Verification, with strong capabilities in System Verilog, UVM methodology, and test bench construction. Proficient in debugging and ensuring complete verification coverage while collaborating effectively with cross-functional teams.

Highest-signal resume keywords

ASIC Design VerificationSystem VerilogUVM MethodologyTest Bench ConstructionScripting with Perl or Python

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Applicant Tracking System Keywords

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Hard Skills

ASIC DesignDesign VerificationTest PlansTest CasesDebuggingFunctional CoverageConstrained Random DV EnvironmentsVeloceHAPSSystemVerilog Constraints

Soft Skills

Effective Communication

Certifications & Qualifications

Bachelor's Degree

Industry Keywords

ASIC EngineeringVerificationSimulationEmulationSoC

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Maintain and enhance existing design verification environments
Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks
Write test plans and develop test cases
Debug regression failures and drive module verification closure
Ensure complete verification coverage through implementation and review of code and functional coverage
Collaborate with verification engineers, designers, hardware, and other cross-functional teams
Verify ASICs in simulation, emulation, and during ASIC bring-up

Requirements

What you’ll need

A Bachelor's degree completed within the past 3 years or expected within the next 12 months
Qualifying education and work experience in ASIC Design, Design Verification, or a related field
Qualifying education and work experience in ASIC Engineering, Verification, or a related field
Experience with System Verilog and UVM methodology
Experience with scripting using Perl and/or Python
Preferred: experience verifying complex ASIC blocks and/or clusters using UVM and SystemVerilog
Preferred: experience with functional coverage and constrained random DV environments
Preferred: experience verifying complex blocks, clusters, and top level for SoC
Preferred: experience with Veloce/HAPS
Preferred: experience building test benches from scratch, including SystemVerilog constraints, structures, and classes
Effective verbal and written communication skills

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco’s policies