ASIC Design Verification Engineer II

Cisco

. Maintain and enhance existing design-verification environments .

Posted 9/18/2026full-timeSan Jose • California • United StatesJuniorMid-LevelWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ASIC Verification, including the construction of test benches and debugging regression failures. Proficient in SystemVerilog, UVM methodology, and scripting with Perl and Python to ensure complete verification coverage.

Highest-signal resume keywords

ASIC VerificationSystemVerilogUVM MethodologyTest Bench ConstructionScripting with Perl and Python

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

ASIC EngineeringVerificationTest PlansTest CasesDebuggingFunctional CoverageConstrained-Random DVVeloce/HAPSSystemVerilog ConstraintsSystemVerilog Structures

Soft Skills

Effective Communication

Tools & Technologies

SimulationEmulationCisco Hardware Platforms

Industry Keywords

Design-VerificationCross-Functional CollaborationComplex ASIC BlocksSoC Verification

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Maintain and enhance existing design-verification environments
Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks
Write test plans and develop test cases
Debug regression failures and drive module verification closure
Ensure complete verification coverage through implementation and review of code and functional coverage
Collaborate with verification engineers, designers, hardware, and other cross-functional teams
Verify ASICs in simulation, emulation, and during ASIC bring-up
Help guarantee seamless integration and optimal performance of Cisco hardware platforms

Requirements

What you’ll need

Meet one of the following, completed within the past 3 years or expected within the next 12 months: Master's degree with 0 years of work experience, or Bachelor's degree with 2 years of work experience
Qualifying education and work experience in ASIC Engineering, Verification, or a related field
Experience with SystemVerilog and UVM methodology
Experience with scripting using Perl and/or Python
Preferred: experience using UVM and SystemVerilog for ASIC verification and verifying complex ASIC blocks and/or clusters
Preferred: experience with functional coverage and constrained-random DV environments
Preferred: experience verifying complex blocks, clusters, and top level for SoC
Preferred: experience with Veloce/HAPS
Preferred: experience building test benches from scratch, including SystemVerilog constraints, structures, and classes
Effective verbal and written communication skills

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to continued employment and vesting periods
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid employee birthday day off
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees, subject to availability and business limitations
80 hours of sick time provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward annually
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies
Performance-based incentive pay for sales-plan employees