ASIC DFT DV Technical Leader

Cisco

. Plan tests and develop testbenches to verify comprehensive DFT architecture .

Posted 10/13/2026full-timeSan Jose • California • United StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in developing and verifying DFT architectures, including test planning and testbench development using SystemVerilog. Proficient in debugging and collaborating with cross-functional teams to ensure high-quality silicon validation.

Highest-signal resume keywords

Test PlanningSystemVerilog DevelopmentDebugging with DVE/VerdiTCL, Python, or Perl ExperienceDFT Verification Leadership

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Test PlanningSystemVerilogDebuggingTCLPythonPerlUVMJTAG ProtocolScan ArchitectureBoundary Scan

Soft Skills

Problem SolvingCollaborationMentorship

Tools & Technologies

DVEVerdi

Industry Keywords

DFT ArchitectureSilicon ValidationTestbenchesIn-System TestingPost-Silicon Validation

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Plan tests and develop testbenches to verify comprehensive DFT architecture
Support ATE screening, in-system testing, debug, and diagnostics requirements
Collaborate with design, design-verification, and physical-design teams
Integrate and validate test logic throughout implementation and post-silicon validation flows
Develop innovative hardware DFT and test strategies for new silicon device models, bare die, and stacked die
Drive reusable test and debug methodologies and standards
Understand chip architecture with front-end RTL and backend physical-design teams
Lead high-quality DFT verification within the Silicon One development organization

Requirements

What you’ll need

Bachelor’s degree plus 8 years of related experience, or Master’s degree plus 6 years of related experience, or PhD plus 3 years of related experience
Prior experience in test planning based on complex design specifications
Prior experience developing testbenches using SystemVerilog
Experience debugging using DVE/Verdi
Experience with TCL, Python, or Perl
Ability to craft solutions and debug with minimal mentorship
UVM and advanced SystemVerilog knowledge preferred
Knowledge of JTAG protocol, scan architecture, MBIST, and boundary scan preferred

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward annually
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses may be available for non-sales roles
Incentive compensation for sales-plan employees, subject to applicable Cisco plan
Opportunities to grow and build at Cisco
Global team collaboration and development opportunities