ASIC DFT Engineer

Cisco

. Work in the Silicon One development organization as an ASIC DFT Engineer .

Posted 10/2/2026full-timeUnited StatesSeniorLead💰 $139,300 - $203,600 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in ASIC DFT engineering, including the development and integration of DFT features, post-silicon validation, and debugging. Proficient in utilizing EDA tools and methodologies to ensure testability and quality throughout the design cycle.

Highest-signal resume keywords

ASIC DFT EngineeringJTAG ProtocolsDFT CAD DevelopmentVerilog DesignPost-Silicon Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT RequirementsTest ArchitectureMemory BISTBoundary ScanGate-Level SimulationATPGSystemVerilogTest Static Timing AnalysisDebuggingCustom DFT Logic

Soft Skills

CollaborationProblem-SolvingMinimal Mentorship

Tools & Technologies

TestMaxTetramaxTessentPrimeTimeVCSATE PatternsP1687

Certifications & Qualifications

Bachelor's Degree in Electrical EngineeringMaster's Degree in Computer Engineering

Industry Keywords

Silicon EngineeringDFT TrendsChip ArchitectureFull-Chip TestabilityDesign Verification

About the role

Key responsibilities & impact

Work in the Silicon One development organization as an ASIC DFT Engineer
Collaborate with front-end RTL, design verification, backend physical design and multifunctional teams
Understand chip architecture and drive DFT requirements early in the design cycle
Implement hardware DFT features supporting ATE, in-system test, debug and diagnostics
Develop innovative DFT IP and integrate full-chip testability features coordinated in RTL
Enable integration and validation of test logic throughout implementation and post-silicon validation flows
Drive DFT and quality processes through implementation and post-silicon validation
Contribute to physical design signoff activities
Create reusable test and debug strategies for new silicon device models, bare die and stacked die
Craft solutions and debug with minimal mentorship

Requirements

What you’ll need

Bachelor's or Master's Degree in Electrical or Computer Engineering required
At least 7 years of experience
Prior experience with current DFT, test and silicon engineering trends
Prior experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan
Prior experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent tool sets, and PrimeTime
Prior experience with gate-level simulation and debugging using VCS and other simulators
Post-silicon validation and debug experience
Ability to work with ATE patterns and P1687
Ability to craft solutions and debug with minimal mentorship
Verilog design experience, including custom DFT logic and IP integration
Familiarity with functional verification
DFT CAD development experience, including test architecture, methodology and infrastructure
Test static timing analysis experience
Post-silicon validation using DFT patterns
SystemVerilog logic equivalency checking and test-timing validation skills

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid personal wellness days
16 days of paid vacation for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies