ASIC DFT Engineer

Cisco

. Support DFT implementation for ASIC/SoC blocks and subsystems .

Posted 10/27/2026full-timeSan Jose • California • United StatesMid-LevelSenior💰 $155,000 - $222,600 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC DFT implementation and validation, including scan architecture, ATPG, and MBIST. Proficient in scripting with Tcl, Python, or Perl to automate DFT processes and enhance reporting.

Highest-signal resume keywords

ASIC DFT ImplementationSiemens TessentScan ArchitectureATPG Pattern GenerationDebugging DFT Violations

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT Logic ImplementationScan InsertionScan CompressionOCCMBISTBoundary ScanFault ModelsDFT Rule ChecksPattern SimulationHierarchical DFT Methodology

Soft Skills

CollaborationProblem-SolvingCommunication

Tools & Technologies

Synopsys DFT CompilerTestMAXTclPythonPerlShell Scripting

Industry Keywords

ASICSoCTest CoverageYield DebugSilicon DebugAdvanced-Node ASICsNetworking ASICsHigh-Performance SoCsIJTAGIEEE 1500

Tech Stack

Tools & technologies

Node.jsPerlPython

About the role

Key responsibilities & impact

Support DFT implementation for ASIC/SoC blocks and subsystems
Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic
Run DFT rule checks and debug scan, clock, reset, and test-mode issues
Generate and validate ATPG patterns for stuck-at, transition, and other fault models
Analyze test coverage, pattern count, compression results, and ATPG reports
Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues
Work with RTL and verification teams to ensure DFT requirements are implemented correctly
Support block-level and full-chip DFT integration activities
Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable
Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting
Support silicon debug, diagnosis analysis, and yield-learning activities as needed
Document DFT implementation results, known issues, waivers, and signoff status
Collaborate with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams
Help deliver high-quality test coverage and manufacturability for advanced semiconductor designs

Requirements

What you’ll need

Bachelor’s degree plus 5 years of related experience, or Master’s degree plus 3 years of related experience, or PhD plus 0 years of related experience, or equivalent related work experience
Experience with ASIC DFT implementation or validation
Experience with Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent DFT tools
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
Experience with stuck-at and transition fault models
Experience debugging DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures
Scripting experience using Tcl, Python, Perl, or shell
Preferred: experience with hierarchical DFT methodology and block-level signoff
Preferred: exposure to IJTAG/IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows
Preferred: experience with MBIST insertion, memory test validation, or BISR flows
Preferred: familiarity with gate-level simulation, SDF timing, and pattern validation
Preferred: exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug
Preferred: experience with advanced-node ASICs, networking ASICs, or high-performance SoCs
Preferred: ability to improve automation, regression checks, and DFT reporting dashboards
Preferred: experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation
Preferred: experience troubleshooting ASIC DFT problems and working with cross-functional teams

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward annually
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses may be available for non-sales roles
Performance-based incentive pay for sales-plan employees
Opportunities to grow and build
Inclusive company culture
Global team collaboration
Professional development and meaningful work opportunities