ASIC DFT Engineer I

Cisco

. Implement hardware Design-for-Test features supporting ATE, in-system test, debug, and diagnostics .

Posted 11/7/2026full-timeUnited StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in hardware Design-for-Test (DFT) implementation, including automation scripting and validation of test logic using SystemVerilog. Proficient in utilizing EDA and ATPG tools for test pattern generation and analysis while collaborating effectively with cross-functional teams.

Highest-signal resume keywords

Hardware Design-For-Test (DFT)SystemVerilogEDA ToolsATPG ToolsScripting in Python

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Automation ScriptingTest Pattern GenerationGate-Level SimulationsDebuggingJTAG ProtocolsScan ArchitecturesBISTLogic Equivalency CheckingTest-Timing ValidationVLSI Circuit Understanding

Soft Skills

Verbal CommunicationWritten Communication

Tools & Technologies

TestMaxTetramaxTessentPrimeTimeVCS

Industry Keywords

ASIC DFTPost-Silicon ValidationStatic Timing AnalysisElectromigrationTemperature VariationVoltage VariationSetup/Hold TimesMetastability

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Implement hardware Design-for-Test features supporting ATE, in-system test, debug, and diagnostics
Create and enhance automation scripts to improve implementation robustness and efficiency
Work with Design, Design Verification, and Physical Design teams to integrate and validate test logic throughout implementation and post-silicon validation flows
Collaborate with team members to validate test timing and logic equivalency using SystemVerilog
Use ATPG and EDA tools, including TestMax, Tetramax, Tessent, and PrimeTime, for test pattern generation and analysis
Understand chip architecture and drive DFT requirements early in the design cycle with frontend RTL and backend Physical Design teams

Requirements

What you’ll need

Bachelor's degree completed within the past 3 years or expected within the next 12 months
Qualifying education in ASIC DFT or a related field
Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST, including memory BIST and boundary scan
Familiarity or introductory hands-on exposure to EDA and ATPG tools
Scripting or coding skills in Python, Tcl, or Perl
Experience with gate-level simulations and debugging using simulators such as VCS
Preferred: practical experience or strong coursework in SystemVerilog, logic equivalency checking, and test-timing validation
Preferred: understanding of basic VLSI circuit physical behaviors, including electromigration and temperature/voltage variation effects
Preferred: familiarity with setup/hold times and metastability
Preferred: exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis
Preferred: strong verbal and written communication skills

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1 thereafter
Up to 80 hours of unused sick time carried forward annually
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses may be available for non-sales roles