ASIC DFT Engineering Technical Leader

Cisco

. Serve as an ASIC Implementation Technical Lead focused primarily on Design-for-Test .

Posted 10/22/2026full-timeUnited StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC Implementation with a strong focus on Design-for-Test (DFT) processes, including experience in Verilog design, ATPG, and EDA tools. Proven ability to lead DFT requirements and support post-silicon validation while collaborating with cross-functional teams.

Highest-signal resume keywords

ASIC ImplementationDesign-For-Test (DFT)Verilog DesignATPG and EDA ToolsPost-Silicon Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Verilog DesignATPGGate-Level SimulationDebugging with VCSScan InsertionScripting in TclScripting in PythonScripting in PerlStatic Timing AnalysisTiming Closure

Tools & Technologies

TestMaxTetramaxTessentJTAG ProtocolsP1500P1687

Industry Keywords

ASICDFT RequirementsChip ArchitecturePhysical DesignPost-Silicon Validation

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Serve as an ASIC Implementation Technical Lead focused primarily on Design-for-Test
Work with front-end RTL and backend physical design teams to understand chip architecture
Drive DFT requirements early in the design cycle
Help craft next-generation networking chips
Lead the DFT and quality process through the entire implementation flow
Support post-silicon validation phases
Participate in physical design signoff activities
Work with ATE engineers on pattern translation and validation

Requirements

What you’ll need

Bachelor’s degree in Electrical or Computer Engineering and 8+ years of experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of experience, or PhD in Electrical Engineering or Computer Engineering and 3 years of experience
Prior experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, or similar tool sets
Experience with gate-level simulation, including timing-based simulations with SDF
Debugging experience with VCS and other simulators
Prior post-silicon validation and debug experience
Prior experience with scan insertion
Verilog design experience, developing custom DFT logic and IP integration
Familiarity with functional verification
Experience with Tessent
Experience with JTAG protocols (P1500, P1687)
Experience with SSN
Scripting skills in Tcl, Python, or Perl
Experience with test static timing analysis constraint development and timing closure

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco’s policies