ASIC DFT Engineering Technical Leader – ATPG, SCAN, MBIST, JTAG

Cisco

. Define, architect, and design high-performance ASICs .

Posted 10/8/2026full-timeBangalore • IndiaSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ASIC design and verification, with a strong focus on DFT methodologies, electrical planning, and collaboration with cross-functional teams. Proficient in scripting and EDA tools to drive high-performance chip development from conception to production.

Highest-signal resume keywords

ASIC DesignDFT MethodologiesJTAG ProtocolsScripting in Tcl, Python, or PerlPost-Silicon Validation

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

ASIC DesignDFT MethodologiesJTAG ProtocolsScan InsertionBIST ArchitecturesATPGGate-Level SimulationStatic Timing AnalysisDebugging with VCSElectrical Planning

Soft Skills

CollaborationLeadershipStakeholder Coordination

Tools & Technologies

TestMaxTetramaxTessentEDA ToolsVCS

Certifications & Qualifications

Bachelor's Degree in Electrical EngineeringMaster’s Degree in Electrical Engineering

Industry Keywords

Physical DesignTiming ClosureFunctional VerificationNext-Generation Networking Chips

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Define, architect, and design high-performance ASICs
Own applications or multiple complex functional areas
Oversee reusable code and its applications
Create reusable code that promotes efficiency
Define verification strategies
Coordinate with stakeholders to integrate into physical design and design verification flows
Own infrastructure and testing environments
Lead and design building blocks of multiple channels
Apply and drive design methodology from conception to production
Collaborate with teams to ensure specifications and requirements are met
Lead technical expertise of a physical design function
Interface with vendors and design leads on full-chip timing closure, PI, and PV
Own electrical planning and specifications for electrical interfaces
Develop multiple solutions and first test vehicles
Perform verification and validation
Drive DFT and quality processes through implementation and post-silicon validation phases
Work with front-end RTL and backend physical design teams to define early DFT requirements
Contribute to next-generation networking chip development

Requirements

What you’ll need

Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
At least 12+ years of experience
Prior experience with JTAG protocols (P1500, P1687)
Experience with scan insertion and BIST architectures, including memory BIST and boundary scan
Experience with ATPG and EDA tools such as TestMax, Tetramax, and Tessent tool sets
Test static timing analysis constraints development and timing closure experience
Experience with gate-level simulation, including timing-based simulations with SDF
Debugging experience with VCS and other simulators
Post-silicon validation and debug experience
Ability to work with ATE engineers on pattern translation and validation
Scripting skills in Tcl, Python, or Perl
Preferred: Verilog design experience, custom DFT logic and IP integration, familiarity with functional verification
Preferred: DFT CAD development, test architecture, methodology, and infrastructure

Benefits

Comp & perks

Hybrid work arrangement
Opportunities to grow and build limitless careers
Collaboration with worldwide network of experts
Work on groundbreaking next-generation networking chips
Exposure to physical design signoff activities
Global-scale impact and innovation opportunities