ASIC DFT Technical Leader

Cisco

. Collaborate closely with front-end RTL and backend physical design teams to understand chip architecture .

Posted 10/19/2026full-timeUnited StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in ASIC digital design with a strong focus on Verilog/SystemVerilog coding, front-end tools, and industry-standard interface protocols. Proven ability to deliver high-quality silicon solutions through collaboration with cross-functional teams and implementation of advanced testing methodologies.

Highest-signal resume keywords

ASIC Digital DesignVerilog/SystemVerilog CodingFront-End ToolsIndustry-Standard Interface ProtocolsPower Optimization Techniques

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC Digital DesignVerilog/SystemVerilog CodingPower Optimization TechniquesDFT/MBISTPost-Silicon Debug

Soft Skills

CollaborationProblem-Solving

Tools & Technologies

Verilog SimulatorsLintingCDC CheckersSynthesisFormal Verification

Industry Keywords

AMBAAXIAPBAHBJTAG

About the role

Key responsibilities & impact

Collaborate closely with front-end RTL and backend physical design teams to understand chip architecture
Drive high-quality structural test, functional test, and diagnostic feature implementation
Develop and integrate intellectual property (IP)
Implement test access, including high-speed I/O with protocols
Deliver robust and reliable silicon solutions meeting Cisco performance and innovation standards
Contribute to advanced networking silicon aligned with Cisco Silicon One’s scalable and flexible architecture

Requirements

What you’ll need

10+ years of industry experience in ASIC digital design
Prior experience in Verilog/SystemVerilog coding
Prior experience with front-end tools, including Verilog simulators, linting, CDC checkers, synthesis, and formal verification
Prior experience with industry-standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories
Experience with power optimization techniques, power intent (UPF), and power estimation preferred
Experience with DFT/MBIST preferred
Experience with post-silicon debug preferred

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to continued employment and vesting periods
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees, subject to availability and business limitations
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid days per full calendar year to volunteer
Annual bonuses for non-sales roles, subject to Cisco’s policies
Performance-based incentive pay for sales-plan employees, subject to the applicable Cisco plan