ASIC DFT Technical Leader

Cisco

. Work in Cisco's Silicon One development organization as an ASIC Technical Leader specializing in DFT .

Posted 10/19/2026full-timeUnited StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in ASIC design with a focus on DFT processes, including JTAG protocols and post-silicon validation. Proficient in collaborating with cross-functional teams to drive quality and efficiency in chip development.

Highest-signal resume keywords

DFT Requirements DevelopmentJTAG ProtocolsPost-Silicon ValidationVerilog DesignATPG and EDA Tools

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

DFTSilicon EngineeringGate-Level SimulationCustom DFT Logic DevelopmentSystemVerilogMemory BISTBoundary ScanTestMaxTetramaxTessent

Tools & Technologies

VCSPrimeTimeATE PatternsP1687

Certifications & Qualifications

Bachelor's Degree in Electrical EngineeringMaster's Degree in Computer Engineering

Industry Keywords

ASICChip ArchitecturePhysical DesignDFT CAD DevelopmentFunctional Verification

About the role

Key responsibilities & impact

Work in Cisco's Silicon One development organization as an ASIC Technical Leader specializing in DFT
Collaborate with front-end RTL and backend physical design teams to understand chip architecture
Drive DFT requirements early in the design cycle
Help lead DFT and quality processes throughout the implementation flow and post-silicon validation phases
Contribute to next-generation networking chip development
Participate in physical design signoff activities
Perform post-silicon validation and debug

Requirements

What you’ll need

Bachelor's or Master's Degree in Electrical or Computer Engineering required
At least 10 years of experience
Prior experience with current DFT, test, and silicon engineering trends
Experience with JTAG protocols, scan and BIST architectures, including memory BIST and boundary scan
Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime
Experience with gate-level simulation and debugging using VCS and other simulators
Post-silicon validation and debug experience
Ability to work with ATE patterns and P1687
Verilog design experience, custom DFT logic development, and IP integration
Familiarity with functional verification
DFT CAD development, including test architecture, methodology, and infrastructure
Test static timing analysis
Post-silicon validation using DFT patterns
SystemVerilog logic equivalency checking and test-timing validation

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, vesting following continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses may be available for non-sales roles