ASIC Digital Design Tech Lead

. Architect next-generation optical interconnects for Silicon One Optics .

Posted 10/23/2026full-timeUnited StatesSenior💰 $166,300 - $238,300 per yearWebsite

Key responsibilities & impact

Architect next-generation optical interconnects for Silicon One Optics
Own the full ASIC lifecycle from initial concept through tapeout and post-silicon production
Lead cross-functional engineering teams across digital, analog, firmware, and physical design
Define digital architectures
Integrate high-speed IP including ODSP, D2D IP, and SerDes XSR/PAM4
Optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics
Drive technical strategy and interconnect innovation
Deliver silicon for high-performance computing
Develop specifications and microarchitectures for high-speed datapaths and low-speed control planes
Support verification, simulation, IP integration, backend implementation, and automation activities

What you’ll need

Bachelor’s degree plus 8 years of related experience, or Master’s degree plus 6 years of related experience, or PhD plus 3 years of related experience
Prior digital design experience with FSMs, CPU sub-systems, complex SoCs, and FPGA validation
Prior experience managing the complete ASIC/SoC design flow
Experience with SPI, I2C, APB, AXI, high-speed SerDes, Ethernet, and D2D PHY IP
Experience leading complex digital block and CPU subsystem architecture and design from pre-silicon RTL to GDS2 signoff
Experience with post-silicon FPGA prototyping, lab validation, and ATE bring-up
Experience developing top- and block-level specifications for high-speed datapaths and low-speed control planes
Experience with power/timing budgeting, feedback/control system stability, and hardware-versus-firmware trade-offs
Experience reviewing verification coverage metrics and debugging verification issues
Experience supporting firmware-based verification/architecture and integrating SerDes and DSP IP
Hands-on experience with synthesis, timing closure, DFT, low-power design, design automation scripting, and QoR metric processing
Experience collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, vesting following continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco’s policies
Performance-based incentive pay for sales-plan employees