ASIC Engineering Technical Leader

. Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes .

Posted 10/24/2026full-timeSan Jose • California • United StatesSenior💰 $186,900 - $267,700 per yearWebsite

Tools & technologies

Python

Key responsibilities & impact

Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes
Drive hierarchical floorplanning and complex mixed-signal macro placement
Perform signoff including STA, IR/EM, and PV to ensure first-pass silicon success
Architect and scale digital implementation flows
Develop custom TCL/Python automation and partner with EDA vendors
Improve quality of results, turnaround time, and team-wide productivity
Lead physical execution across PnR, CTS, MMMC timing closure, and ECO iterations
Collaborate with RTL, Analog, DFT, Packaging, and CAD teams to resolve cross-domain bottlenecks
Develop physical designs for 800G, 1.6T, and multi-terabit optical transceivers and driver ICs

What you’ll need

Bachelor's degree plus 8 years of related experience, or Master's degree plus 6 years of related experience, or PhD plus 3 years of related experience
Prior experience in ASIC/SoC physical design and implementation in advanced technology nodes
Hands-on experience with the full physical design flow at block and/or chip level
Hands-on expertise with EDA tool flows and back-end sign-off criteria
Workflow automation experience using Python, TCL, and Shell scripts
Preferred: experience closing high-speed, high-density, macro-dominant, and I/O cell-intensive blocks
Preferred: expertise in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation
Preferred: ability to identify, debug, and fix EM, IR drop, RC parasitic extraction, and crosstalk/glitch violations
Preferred: hands-on experience with functional equivalence checking and functional ECOs
Preferred: experience in power grid design and optimization
Preferred: understanding of standard-cell IP and memory compiler IP selection
Preferred: experience integrating mixed-signal designs

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Grants of Cisco restricted stock units, subject to eligibility
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid personal wellness days
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies