ASIC Packaging SI/PI Engineer

Cisco

. Develop, document, and implement design rules for ultra-high-speed signaling .

Posted 11/7/2026full-timeSan Jose • California • United StatesJuniorMid-Level💰 $125,700 - $176,600 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in high-speed signaling design, including power and signal integrity analysis, and proficiency with EDA tools for ASIC packaging. Capable of collaborating effectively with cross-functional teams to achieve design goals and resolve complex technical challenges.

Highest-signal resume keywords

High-Speed Design PrinciplesSignal Integrity AnalysisPower Integrity AnalysisEDA Tools ProficiencyASIC Packaging Development

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Transmission Line TheoryElectromagneticsScattering ParametersImpedance Network Analysis56G PAM4 SerDes ArchitecturesChannel ModelingBER PredictionSI/PI CharacterizationImpedance ProfilingInsertion/Return Loss Analysis

Soft Skills

Technical Communication

Tools & Technologies

Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EMVNATDRHigh-Bandwidth OscilloscopesSpectrum AnalyzersNetwork Analyzers

Industry Keywords

High-Speed SignalingASIC PackagingPower Delivery NetworkCoWoSEMIBInterposer-Based DesignsUCIeDie-to-Die InterfacesLaboratory CharacterizationComplex Technical Issues

About the role

Key responsibilities & impact

Develop, document, and implement design rules for ultra-high-speed signaling
Ensure product power, performance, and area goals are met
Analyze substrate signal integrity and power integrity
Collaborate with layout teams across interposer, substrate, and PCB designs
Design, document, and develop ASIC packages for high-volume, high-quality release
Perform post-layout extraction and reporting
Collaborate with system partners, vendors, and design leads
Achieve combined power and signal integrity objectives
Resolve complex technical issues using advanced technology design rules
Help define, design, and verify next-generation ASIC packaging for Cisco platforms

Requirements

What you’ll need

Bachelor's degree plus 2 years of related experience, or Master's degree plus 0 years of related experience
Experience with high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis
Experience applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
Experience in pre- and post-layout signal and power integrity analysis
Experience with EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
Experience with physical validation using Cadence APD and Ansys EM flows
Experience with laboratory measurements using VNA, TDR, and related instruments
Experience planning and executing SI/PI measurements and laboratory characterization
Experience with impedance profiling, insertion/return loss analysis, and full channel characterization
Experience performing SI/PI characterization, validation, and debugging of high-speed systems and packages
Experience using high-bandwidth oscilloscopes, spectrum analyzers, network analyzers, and probe stations
Must live within commuting distance of the San Jose, CA office and commute at least 4–5 days per week
Preferred: experience articulating technical concepts to diverse audiences
Preferred: experience with HBM or high-speed memory interface SI
Preferred: experience with UCIe or proprietary die-to-die interfaces
Preferred: experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs
Preferred: experience developing and executing high-speed interface test plans and correlating measurements with simulations
Preferred: experience analyzing S-parameters, channel characteristics, crosstalk, reflections, impedance discontinuities, and power delivery network performance
Preferred: experience collaborating across ASIC, package, board, and system engineering teams

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward annually
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies
Hybrid work arrangement