ASIC Packaging Signal/Power Integrity Hardware Engineer

Cisco

. Develop, document, and implement design rules for ultra-high-speed signaling .

Posted 10/8/2026full-timeSan Jose • California • United StatesMid-LevelSenior💰 $155,000 - $222,600 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in signal and power integrity analysis, high-speed design principles, and ASIC packaging development. Proficient in using EDA tools for simulations and validations to achieve optimal performance in high-volume product releases.

Highest-signal resume keywords

Signal Integrity AnalysisPower Integrity AnalysisHigh-Speed Design PrinciplesEDA Tools ProficiencyASIC Packaging Development

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Signal IntegrityPower IntegrityTransmission Line TheoryElectromagnetics56G PAM4 SerDes ArchitecturesSPICEChannel ModelingBER PredictionLayout ReviewsPhysical Design Validation

Soft Skills

Technical Communication

Tools & Technologies

Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM

Industry Keywords

High-Bandwidth MemoryDie-to-Die InterfacesCoWoSEMIBInterposer-Based Designs2.5D ASIC PackagingVector Network AnalysisIBIS

About the role

Key responsibilities & impact

Develop, document, and implement design rules for ultra-high-speed signaling
Ensure power, performance, and area goals are met for products
Analyze substrate signal integrity and power integrity
Collaborate with the layout team to develop optimal solutions across interposer, substrate, and PCB
Design, document, and develop ASIC packages for high-volume, high-quality release
Perform post-layout extraction and reporting
Collaborate with system partners, vendors, and design leads
Achieve combined power and signal integrity objectives
Resolve complex technical issues using advanced technology design rules
Help define, design, and verify next-generation ASIC packaging for Cisco platforms

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master’s degree in Electrical Engineering and 2+ years of relevant experience, or PhD in Electrical Engineering and 0+ years of related experience, or equivalent related work experience
Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis
Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
Experience with pre- and post-layout SI/PI simulations using EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation
Preferred: articulating technical concepts to diverse audiences verbally and in writing
Preferred: high-bandwidth memory or high-speed memory interface SI experience
Preferred: die-to-die interfaces such as UCIe or proprietary interfaces
Preferred: advanced packaging including CoWoS, EMIB, and interposer-based designs
Preferred: SI/PI analysis of 2.5D ASIC packaging
Preferred: Vector Network Analysis
Preferred: IBIS

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to continued employment and vesting periods
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies